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intel ? 810 chipset: intel ? 82810/82810-dc100 graphics and memor y controller hub ( gmch ) datasheet june 1999 order number: 290656-002 r
intel ? 82810/82810-dc100 (gmch) r 2 datasheet information in this document is provided in connection with intel products. no license, express or implied, by estoppel or oth erwise, to any intellectual property rights is granted by this document. except as provided in intels terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the intel ? 810 and intel ? 810-dc100 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. i 2 c is a 2-wire communications bus/protocol developed by philips. smbus is a subset of the i 2 c bus/protocol and was developed by intel. implementations of the i 2 c bus/protocol may require licenses from various entities, including philips electronics n.v. and north american philips corpor ation. alert on lan is a result of the intel-ibm advanced manageability alliance and a trademark of ibm copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtain ed from: intel corporation or call 1-800-548-4725 *third-party brands and names are the property of their respective owners. copyright ? intel corporation 1998, 1999
r intel ? 82810/82810-dc100 (gmch) datasheet 3 contents 1. overview..................................................................................................................... ................ 11 1.1. the intel ? 810 chipset system ..................................................................................... 11 1.2. gmch overview............................................................................................................ 14 1.3. host interface ............................................................................................................. ... 15 1.4. system memory interface.............................................................................................. 15 1.5. display cache interface (82810-dc100 only)............................................................... 15 1.6. hub interface .............................................................................................................. ... 15 1.7. gmch graphics support............................................................................................... 16 1.7.1. display, digital video out, and lcd/flat panel ................................................ 16 1.8. system clocking ............................................................................................................ 17 1.9. references ................................................................................................................. ... 17 2. signal description........................................................................................................... ............ 19 2.1. host interface signals.................................................................................................... 2 0 2.2. system memory interface signals ................................................................................. 21 2.3. display cache interface signals (82810-dc100 only)................................................... 22 2.4. hub interface signals .................................................................................................... 22 2.5. display interface signals ............................................................................................... 23 2.6. digital video output signals/tv-out pins ..................................................................... 24 2.7. power signals .............................................................................................................. .. 25 2.8. clock signals .............................................................................................................. ... 25 2.9. miscellaneous interface signals .................................................................................... 26 2.10. power-up/reset strap options (82810) ........................................................................ 26 2.11. power-up/reset strap options (82810-dc100)............................................................ 26 3. configuration registers ...................................................................................................... ........ 27 3.1. register nomenclature and access attributes .............................................................. 27 3.2. pci configuration space access................................................................................... 28 3.2.1. pci bus configuration mechanism ................................................................... 28 3.2.2. logical pci bus #0 configuration mechanism.................................................. 29 3.2.3. primary pci (pci0) and downstream configuration mechanism ..................... 29 3.2.4. internal graphics device configuration mechanism......................................... 29 3.2.5. gmch register introduction ............................................................................. 29 3.3. i/o mapped registers.................................................................................................... 30 3.3.1. config_address ? configuration address register ................................... 30 3.3.2. config_data ? configuration data register ................................................ 31 3.4. host-hub interface bridge/dram controller device registers (device 0) ................... 31 3.4.1. vid ? vendor identification register (device 0) ................................................ 33 3.4.2. did ? device identification register (device 0) ................................................ 33 3.4.3. pcicmd ? pci command register (device 0)................................................. 33 3.4.4. pcists ? pci status register (device 0) ........................................................ 35 3.4.5. rid ? revision identification register (device 0).............................................. 36 3.4.6. subc ? sub-class code register (device 0) .................................................. 36 3.4.7. bcc ? base class code register (device 0) ................................................... 36 3.4.8. mlt ? master latency timer register (device 0)............................................. 37 3.4.9. hdr ? header type register (device 0) .......................................................... 37
intel ? 82810/82810-dc100 (gmch) r 4 datasheet 3.4.10. svid ? subsystem vendor identification register (device 0) .......................... 37 3.4.11. sid ? subsystem identification register (device 0) ......................................... 38 3.4.12. capptr ? capabilities pointer (device 0) ....................................................... 38 3.4.13. gmchcfg ? gmch configuration register (device 0) .................................. 39 3.4.14. pamr?programmable attributes register (device 0) .................................... 40 3.4.15. drp ? dram row population register (device 0) .......................................... 41 3.4.16. dramt ? dram timing register (device 0) ................................................... 43 3.4.17. fchc ? fixed dram hole control register (device 0)................................... 44 3.4.18. smram ? system management ram control register (device 0) ................ 45 3.4.19. miscc ? miscellaneous control register (device 0) ....................................... 47 3.4.20. miscc2 ? miscellaneous control 2 register (device 0) .................................. 48 3.4.21. buff_sc?system memory buffer strength control register (device 0) ...... 49 3.5. graphics device registers ? (device 1) ....................................................................... 51 3.5.1. vid ? vendor identification register (device 1) ............................................... 52 3.5.2. did ? device identification register (device 1)................................................ 52 3.5.3. pcicmd ? pci command register (device 1) ................................................ 53 3.5.4. pcists ? pci status register (device 1) ........................................................ 54 3.5.5. rid ? revision identification register (device 1) ............................................. 55 3.5.6. pi-programming interface register (device 1) ................................................ 55 3.5.7. subc1sub-class code register (device 1) ................................................ 55 3.5.8. bcc1base class code register (device 1)................................................. 56 3.5.9. cls ? cache line size register (device 1) ..................................................... 56 3.5.10. mlt ? master latency timer register (device 1) ............................................ 56 3.5.11. hdr ? header type register (device 1).......................................................... 57 3.5.12. bist ? built in self test (bist) register (device 1) ........................................ 57 3.5.13. gmadr ? graphics memory range address register (device 1) .................. 58 3.5.14. mmadr ? memory mapped range address register (device 1).................... 59 3.5.15. svid ? subsystem vendor identification register (device 1) .......................... 59 3.5.16. sid ? subsystem identification register (device 1) ......................................... 60 3.5.17. romadr ? video bios rom base address registers (device 1)................ 60 3.5.18. cappoint ? capabilities pointer register (device 1)..................................... 60 3.5.19. intrline ? interrupt line register (device 1)................................................. 61 3.5.20. intrpin ? interrupt pin register (device 1) .................................................... 61 3.5.21. mingnt ? minimum grant register (device 1) ............................................... 61 3.5.22. maxlat ? maximum latency register (device 1) .......................................... 61 3.5.23. pm_capid ? power management capabilities id register (device 1) ........... 62 3.5.24. pm_cap ? power management capabilities register (device 1).................... 62 3.5.25. pm_cspower management control/status register (device 1)................. 63 3.6. display cache interface (82810-dc100 only) .............................................................. 64 3.6.1. drtdram row type ................................................................................... 64 3.6.2. dramcldram control low ........................................................................ 65 3.6.3. dramchdram control high....................................................................... 66 3.7. display cache detect and diagnostic registers (82810-dc100 only)........................ 67 3.7.1. grx ? grx graphics controller index register .............................................. 67 3.7.2. msr ? miscellaneous output ........................................................................... 68 3.7.3. gr06 ? miscellaneous register ....................................................................... 69 3.7.4. gr10 ? address mapping................................................................................. 70 3.7.5. gr11 ? page selector ...................................................................................... 70
r intel ? 82810/82810-dc100 (gmch) datasheet 5 4. functional description ....................................................................................................... ......... 71 4.1. system address map..................................................................................................... 71 4.1.1. memory address ranges.................................................................................. 71 4.1.1.1. compatibility area ................................................................................ 72 4.1.1.2. extended memory area........................................................................ 74 4.1.1.3. system management mode (smm) memory range ............................ 76 4.1.2. memory shadowing .......................................................................................... 76 4.1.3. i/o address space ............................................................................................ 77 4.1.4. gmch decode rules and cross-bridge address mapping ............................. 77 4.2. host interface ............................................................................................................. ... 78 4.2.1. host bus device support .................................................................................. 78 4.2.2. special cycles................................................................................................... 81 4.3. system memory dram interface .................................................................................. 82 4.3.1. dram organization and configuration............................................................. 82 4.3.1.1. configuration mechanism for dimms.................................................. 83 4.3.1.2. dram register programming.............................................................. 84 4.3.2. dram address translation and decoding ....................................................... 84 4.3.3. dram array connectivity.................................................................................. 86 4.3.4. sdramt register programming...................................................................... 86 4.3.5. sdram paging policy....................................................................................... 87 4.4. intel a dynamic video memory technology (d.v.m.t.) .................................................. 87 4.5. display cache interface (82810-dc100 only)............................................................... 87 4.5.1. supported dram types ................................................................................... 88 4.5.2. memory configurations ..................................................................................... 88 4.5.3. address translation .......................................................................................... 89 4.5.4. display cache interface timing ........................................................................ 89 4.6. internal graphics device ............................................................................................... 90 4.6.1. 3d/2d instruction processing ........................................................................... 90 4.6.2. 3d engine ......................................................................................................... 91 4.6.3. buffers............................................................................................................... 91 4.6.4. setup................................................................................................................. 93 4.6.5. texturing ........................................................................................................... 93 4.6.6. 2d operation..................................................................................................... 95 4.6.7. fixed blitter (blt) and stretch blitter (strblt) engines ................................ 95 4.6.7.1. fixed blt engine................................................................................. 96 4.6.7.2. arithmetic stretch blt engine ............................................................. 96 4.6.8. hardware motion compensation....................................................................... 96 4.6.9. hardware cursor............................................................................................... 97 4.6.10. overlay engine.................................................................................................. 97 4.6.11. display............................................................................................................... 97 4.6.12. flat panel interface / 1.8v tv-out interface..................................................... 99 4.6.13. ddc (display data channel) .......................................................................... 100 4.7. system reset for the gmch ....................................................................................... 101 4.8. system clock description............................................................................................ 101 4.9. power management..................................................................................................... 101 4.9.1. specifications supported ................................................................................ 101 5. pinout and package information .............................................................................................. 1 03 5.1. 82810 and 82810-dc100 gmch pinout ..................................................................... 103 5.2. package dimensions ................................................................................................... 109
intel ? 82810/82810-dc100 (gmch) r 6 datasheet 6. testability.................................................................................................................. ............... 111 6.1. xor tree testability algorithm example ................................................................. 112 6.1.1. test pattern consideration for xor chain 7 ................................................. 112 6.2. xor tree initialization ................................................................................................ 113 6.2.1. chain [1:2, 4:7] initialization............................................................................ 113 6.2.2. chain 3 initialization........................................................................................ 113 6.3. xor chain pin assignments ...................................................................................... 114
r intel ? 82810/82810-dc100 (gmch) datasheet 7 figures figure 1. intel ? 810 chipset system block diagram with intel 82810 gmch and either ich or ich0 ....................................................................................................12 figure 2. intel ? 810 chipset system block diagram with intel 82810-dc100 gmch and ich.....................................................................................................................13 figure 3. gmch block diagram...............................................................................................14 figure 4. system memory address map ..................................................................................71 figure 5. detailed memory system address map ....................................................................72 figure 6. gmch graphics register memory address space ..................................................75 figure 7. dram array sockets (2 dimm sockets) ..................................................................86 figure 8. gmch display cache interface to 4mb....................................................................88 figure 9. 3d/2d pipeline preprocessor ....................................................................................90 figure 10. data flow for the 3d pipeline..................................................................................92 figure 11. gmch pinout (top view-left side) ......................................................................104 figure 12. gmch pinout (top view-right side) ....................................................................105 figure 13. gmch package dimensions (421 bga) C top and side views ..........................109 figure 14. gmch package dimensions (421 bga) C bottom view ......................................110 figure 15. xor tree implementation ....................................................................................111 tables table 1. power-up options (82810).........................................................................................26 table 2. power-up options (82810-dc100) ............................................................................26 table 3. gmch pci configuration space (device 0) ..............................................................32 table 4. programming dram row population register fields ...............................................42 table 5. gmch configuration space (device 1) .....................................................................51 table 6. memory map for 03000hC0ffffh address offset range.........................................64 table 7. memory segments and their attributes ......................................................................73 table 8. summay of transactions supported by gmch.........................................................79 table 9. host responses supported by the gmch.................................................................80 table 10. special cycles ....................................................................................................... ...81 table 11. sample of possible mix and match options for 4 row/2 dimm configurations ....83 table 12. data bytes on dimm used for programming dram registers ...............................84 table 13. gmch dram address mux function ......................................................................85 table 14. programmable sdram timing parameters ............................................................86 table 15. memory size for each configuration........................................................................88 table 16. gmch local memory address mapping..................................................................89 table 17. partial list of display modes supported ..................................................................98 table 18. partial list of flat panel modes supported ..............................................................99 table 19. partial list of tv-out modes supported.................................................................100 table 20. alphabetical pin assignment.................................................................................106 table 21. gmch package dimensions (421 bga) ...............................................................110 table 22. xor test pattern example....................................................................................112 table 23. xor chain 1 .......................................................................................................... 114 table 24. xor chain 2 .......................................................................................................... 114 table 25. xor chain 3 .......................................................................................................... 115 table 26. xor chain 4 .......................................................................................................... 116 table 27. xor chain 5 .......................................................................................................... 117 table 28. xor chain 6 .......................................................................................................... 118 table 29. xor chain 7 .......................................................................................................... 119
intel ? 82810/82810-dc100 (gmch) r 8 datasheet revision history rev. description date -002 editorial changes throughout for clarification updated section 4.4, section 2.6 (clkout[1:0] description), section 2.5 (iref description), added new figure in sectdion 3.6. june 1999 -001 initial release april 1999
r intel ? 82810/82810-dc100 (gmch) datasheet 9 intel ? 82810 and intel ? 82810-dc100 product features ? processor/host bus support ? optimized for the intel celeron tm processor ? supports processor 370-pin socket connector ? supports 32-bit system bus addressing ? 4 deep in-order queue; 4 or 1 deep request queue ? supports uni-processor systems only ? in-order and dynamic deferred transaction support ? 66/100mhz system bus frequency ? agtl+ i/o buffer ? integrated dram controller ? 8 mb to 256 mb using 16mb/64mb technology (512 mb using 128mb technology) ? supports up to 2 double sided dimm modules ? 64-bit data interface ? 100mhz system memory bus frequency ? support for asymmetrical dram addressing only ? support for x8, x16 and x32 dram device width ? refresh mechanism: cbr only supported ? enhanced open page arbitration sdram paging scheme ? suspend to ram support ? integrated graphics controller ? 3d hyper pipelined architecture ? -parallel data processing (pdp) ? -precise pixel interpolation (ppi) ? full 2d h/w acceleration ? motion video acceleration ? 3d graphics visual enhancements ? flat & gouraud shading ? mip maps with bilinear and anisotropic filtering ? fogging atmospheric effects ? z-buffering ? 3d pipe 2d clipping ? backface culling ? 3d graphics texturing enhancements ? per pixel perspective correction texture mapping ? texture compositing ? texture color keying/chroma keying ? digital video output ? 85mhz flat panel monitor interface or digital video output for use with a external tv encoder ? display ? integrated 24-bit 230mhz ramdac ? gamma corrected video ? ddc2b compliant ? 2d graphics ? up to 1600x1200 in 8-bit color at 85 hz refresh ? hardware accelerated functions ? 3 operand raster bitblts ? 64x64x3 color transparent cursor ? arithmetic stretch blitter video ? h/w motion compensation assistance for s/w mpeg2 decode ? software dvd at 30fps ? digital video out port ? ntsc and pal tv out support ? h/w overlay engine with bilinear filtering ? independent gamma correction, saturation, brightness & contrast for overlay ? integrated graphics memory controller ? intel a d.v.m. technology ? display cache interface ( 82810-dc100 only) ? 32-bit data interface ? 100 mhz sdram interface ? support for 1mx16, (4 mb only) ? arbitration scheme and concurrency ? centralized arbitration model for optimum concurrency support ? concurrent operations of processor and system busses supported via dedicated arbitration and data buffering ? data buffering ? distributed data buffering model for optimum concurrency ? dram write buffer with read-around-write capability ? dedicated cpu-dram, hub interf ace-dram and graphics-dram read buffers ? power management functions ? smram space remapping to a 0000h (128 kb) ? optional extended smram space above 256 mb, additional 512k/1mb tseg from top of memory, cacheable ? stop clock grant and halt special cycle translation from the host to the hub interface ? acpi compliant power management ? apic buffer management ? smi, sci, and serr error indication ? supporting i/o bridge ? 241 pin bga i/o controller hub (ich0/ich) ? packaging/power ? 421 bga ? 1.8v core with 3.3v cmos i/o
intel ? 82810/82810-dc100 (gmch) r 10 datasheet gmch simplified block diagram gmch_blk.vsd ha[31:3]# hd[63:0]# ads# bnr# bpri# dbsy# defer# drdy# hit# hitm# hlock# hreq[4:0]# htrdy# rs[2:0]# cpurst# system bus interface smaa[11:0] smab[7:4]# sbs[1:0] smd[63:0] sdqm[7:0] scs[3:0]# sras# scas# swe# scke[1:0] system memory interface display cache interface (82810- dc100 only) lcs# ldqm[3:0]# lsras# lscas# lma[11:0] lwe# lmd[31:0] display interface digital tv out hub interface hubref hl[10:0] hlstrb hlstrb# hcomp vsync hsync iref red green blue ddcscl ddcsda ltvcl ltvda tvclkin/int# clkout[1:0] blank# ltvdata[11:0] tvsync tvhsync clock signals hclk sclk ltclk loclk lrclk dclkref hlclk glrrefa gtlrefb reset# misc. interface signals note: the display cache interface is only avaliable on the 82810-dc100.
r intel ? 82810/82810-dc100 (gmch) datasheet 11 1. overview the intel ? 810 chipset is a high-integration chipset designed for the basic graphics/multimedia pc platform. the chipset consists of a graphics and memory controller hub (gmch) host bridge and an i/o controller hub (ich/ich0) bridge for the i/o subsystem. the gmch integrates a system memory dram controller that supports a 64-bit 100 mhz dram array. the dram controller is optimized for maximum efficiency. there are two versions of the gmch (82810 and 82810-dc100). these two versions are pin compatible. the difference between the two versions is that the 82810dc-100 integrates a display cache dram controller that supports a 4 mb, 32-bit 100 mhz dram array for enhanced 2d and 3d performance. this document describes both versions of the gmch (82810 and 82810-dc100). an overview of the intel ? 810 chipset is provided in the next section. note: in this document the term gmch refers to both the 82810 and 82810-dc100, unless otherwise specified. the intel ? 810 and intel ? 810-dc100 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. 1.1. the intel ? 810 chipset system the intel ? 810 chipset uses a hub architecture with the gmch as the host bridge hub and the 82801xx i/o controller hub (ich) as the i/o hub. the ich is a highly integrated multifunctional i/o controller hub that provides the interface to the pci bus and integrates many of the functions needed in todays pc platforms. the gmch and ich communicate over a dedicated hub interface. like the gmch, there are two versions of the ich (82801aa: ich and 82801ab: ich0). this provides added flexibility in designing cost-effective system solutions. these devices are pin compatible and are in 241-pin packages. the gmch devices are designed to work with either ich or ich0. 82801aa (ich) / 82801ab (ich0) functions and capabilities include: pci rev 2.2 compliant with support for 33 mhz pci operations ich0 supports up to 4 req/gnt pairs (pci slots); ich supports up to 6 req/gnt pairs (pci slots) power management logic support enhanced dma controller, interrupt controller & timer functions integrated ide controller; ich0 supports ultra ata/33; ich also supports ultra ata/66 usb host interface with support for 2 usb ports system management bus (smbus) compatible with most i 2 c devices ac97 2.1 compliant link for audio and telephony codecs low pin count (lpc) interface firmware hub (fwh) interface support alert on lan* (82801aa ich only)
intel ? 82810/82810-dc100 (gmch) r 12 datasheet figure 1and figure 2 show block diagrams of typical platforms based on the intel ? 810 chipset. the gmch supports processor bus frequencies of 66/100 mhz. figure 1 shows a system without a display cache. it uses the intel 82810 gmch and either the ich (82801aa) or ich0 (82801ab). both ich0 and ich provide extensive i/o support. the ich provides additional support for 6 pci bus req/gnt pairs (instead of 4 for the ich0), increased ide capability from ultra ata/33 to ultra ata/66, and alert on lan*. figure 2 shows a system based on the 82810-dc100 gmch that includes a display cache. figure 1. intel ? 810 chipset system block diagram with intel 82810 gmch and either ich or ich0 system bus (66/100 mhz) system memory processor pci bus pci slots (ich = 6 req/gnt pairs) (ich0 = 4 req/gnt pairs) sysblk1.vsd isa option 2 ide ports ich = ultra ata/66 ich0 = ultra ata/33 2 usb ports usb usb intel ? 82810 (gmch0) - memory controller - graphcs controller - 3d engine - 2d engine - video engine tv display encoder 64 bit / 100 mhz only ich and ich0 (i/o controller hub) super i/o ac'97 fwh (firmware hub) intel ? 810 chipset digital video out audio codec modem codec lan option
r intel ? 82810/82810-dc100 (gmch) datasheet 13 figure 2. intel ? 810 chipset system block diagram with intel 82810-dc100 gmch and ich system bus (66/100 mhz) system memory pci bus pci slots (ich=6 req/gnt pairs) sysblk2.vsd isa option 2 ide ports ultra ata/66 2 usb ports usb usb intel ? 82810-dc100 (gmch) - memory controller - graphcs controller - 3d engine - 2d engine - video engine tv display encoder (4 mb sdram, 100 mhz only) display cache 64 bit / 100 mhz only ich (i/o controller hub) super i/o ac'97 fwh (firmware hub) intel ? 810 chipset digital video out audio codec modem codec lan option processor
intel ? 82810/82810-dc100 (gmch) r 14 datasheet 1.2. gmch overview figure 3 is a block diagram of the gmch illustrating the various interfaces and integrated components of the gmch chip. the gmch functions and capabilities include: support for a single processor configuration 64-bit agtl+ based system bus interface at 66 mhz/100 mhz 32-bit host address support 64-bit system memory interface with optimized support for sdram at 100 mhz integrated 2d & 3d graphics engines integrated h/w motion compensation engine integrated 230 mhz dac integrated digital video out port 4 mb display cache (82810-dc100 only) figure 3. gmch block diagram system bus interface buffer memory interface buffer hub interface system memory display cache memory (82810-dc100 only) hw motion comp display en g ine 3d en g ine 3d en g ine dac overla y hw cursor di g ital video out port 2d en g ine stretch blt en g blt en g analo g display out di g ital video out ddc i 2 c gmch_blk2.vsd
r intel ? 82810/82810-dc100 (gmch) datasheet 15 1.3. host interface the host interface of the gmch is optimized to support the intel celeron tm processor. the gmch implements the host address, control, and data bus interfaces within a single device. the gmch supports a 4-deep in-order queue (i.e., supports pipelining of up to 4 outstanding transaction requests on the host bus) . host bus addresses are decoded by the gmch for accesses to system memory, pci memory and pci i/o (via hub interface), pci configuration space and graphics memory. the gmch takes advantage of the pipelined addressing capability of the processor to improve the overall system performance. the gmch supports the 370-pin socket (pga370). this is a zero insertion force (zif) socket that a processor in the ppga package uses to interface with a system board. 1.4. system memory interface the gmch integrates a system memory dram controller that supports a 64-bit 100 mhz dram array. the dram type supported is industry standard synchronous dram (sdram). the dram controller interface is fully configurable through a set of control registers. complete descriptions of these registers are given in the configuration register description section. the gmch supports industry standard 64-bit wide dimm modules with sdram devices. the twelve multiplexed address lines, smaa[11:0], along with the two bank select lines, sbs[1:0], allow the gmch to support 2m, 4m, 8m, and 16m x64 dimms. only asymmetric addressing is supported. the gmch has four scs# lines, enabling the support of up to four 64-bit rows of dram. the gmch targets sdram with cl2 and cl3 and supports both single and double-sided dimms. additionally, the gmch also provides a seven deep refresh queue. the gmch can be configured to keep multiple pages open within the memory array, pages can be kept open in any one row of memory. scke[1:0] is used in configurations requiring powerdown mode for the sdram. 1.5. display cache interface (82810-dc100 only) the 82810-dc100 gmch supports a display cache dram controller with a 32-bit 100 mhz dram array. the dram type supported is industry standard synchronous dram (sdram) like that of the system memory. the local memory dram controller interface is fully configurable through a set of control registers. complete descriptions of these registers are given in the register description section. 1.6. hub interface the hub interface is a private interconnect between the gmch and the ich.
intel ? 82810/82810-dc100 (gmch) r 16 datasheet 1.7. gmch graphics support the graphics and memory controller hub (gmch) includes a highly integrated graphics accelerator. its architecture consists of dedicated multi-media engines executing in parallel to deliver high performance 3d, 2d and motion compensation video capabilities. the 3d and 2d engines are managed by a 3d/2d pipeline preprocessor allowing a sustained flow of graphics data to be rendered and displayed. the deeply pipelined 3d accelerator engine provides 3d graphics quality and performance via per-pixel 3d rendering and parallel data paths that allow each pipeline stage to simultaneously operate on different primitives or portions of the same primitive. the gmch graphics accelerator engine supports perspective-correct texture mapping, bilinear and anisotropic mip-mapping, gouraud shading, alpha- blending, fogging and z-buffering. a rich set of 3d instructions permit these features to be independently enabled or disabled. for the 82810-dc100, a display cache (dc) can be used for z-buffers (textures and display buffer are located in system memory). if the display cache is not used, the z-buffer is located in system memory. the gmch integrated graphics accelerators 2d capabilities include blt and arithmetic strblt engines, a hardware cursor and an extensive set of 2d registers and instructions. the high performance 64-bit bitblt engine provides hardware acceleration for many common windows operations. in addition to its 2d/3d capabilities, the gmch integrated graphics accelerator also supports full mpeg-2 motion compensation for software-assisted dvd video playback, a vesa ddc2b compliant display interface and a digital video out port that may support (via an external video encoder) ntsc and pal broadcast standards. 1.7.1. display, digital video out, and lcd/flat panel the gmch provides interfaces to a standard progressive scan monitor, tv-out device, and lcd/flat panel transmitter. the gmch directly drives a standard progressive scan monitor up to a resolution of 1600x1200. the gmch provides a digital video out interface to connect an external device to drive an autodetection of 1024x768 non-scalar ddp digital flat panel with appropriate edid 1.x data. the interface has 1.8v signaling to allow it to operate at higher frequencies. this interface can also connect to a 1.8v tv-out encoder.
r intel ? 82810/82810-dc100 (gmch) datasheet 17 1.8. system clocking the gmch has a new type of clocking architecture. it has integrated sdram buffers that always run at 100 mhz, regardless of system bus frequency. the system bus frequency is selectable between 66 mhz and 100 mhz. the gmch uses a copy of the usb clock as the dot clock input for the graphics pixel clock pll. 1.9. references intel 810 chipset design gui de (order number 290657) pc 99: contact www.microsoft.com/hwdev agtl+ i/o specification: contained in the pentium ii processor databook pci local bus specification 2.2 : contact www.pcisig.com intel ? 82801aa (ich) and intel ? 82801ab (ich0) i/o controller hub datasheet (order number 290655)
intel ? 82810/82810-dc100 (gmch) r 18 datasheet
r intel ? 82810/82810-dc100 (gmch) datasheet 19 2. signal description this section provides a detailed description of the gmch signals. the signals are arranged in functional groups according to their associated interface. the states of all of the signals during reset are provided in the system reset section. the # symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. when # is not present after the signal name the signal is asserted when at the high voltage level. the following notations are used to describe the signal type: i input pin o output pin i/od input / open drain output pin. this pin requires a pullup to the vcc of the processor core i/o bi-directional input/output pin the signal description also includes the type of buffer used for the particular signal: agtl+ open drain agtl+ interface signal. refer to the agtl+ i/o specification for complete details cmos the cmos buffers are low voltage ttl compatible signals. these are 3.3v only. lvttl low voltage ttl compatible signals. there are 3.3v only. 1.8v 1.8v signals for the digital video interface analog analog crt signals note that the processor address and data bus signals (host interface) are logically inverted signals (i.e., the actual values are inverted versions of what appears on the processor bus). this must be taken into account and the addresses and data bus signals must be inverted inside the gmch. all processor control signals follow normal conventions. a 0 indicates an active level (low voltage) if the signal is followed by a # symbol and a 1 indicates an active level (high voltage) if the signal has no # suffix.
intel ? 82810/82810-dc100 (gmch) r 20 datasheet 2.1. host interface signals signal name type description cpurst# o agtl+ cpu reset. the gmch asserts cpurst# while reset# (pcirst# from ich) is asserted and for approximately 1ms after reset# is deasserted. the gmch also pulses cpurst# for approximately 1ms when requested via a hub interface special cycle. the cpurst# allows the processor to begin execution in a known state. ha[31:3]# i/o agtl+ host address bus: ha[31:3]# connect to the processor address bus. during processor cycles, ha[31:3]# are i nputs. the gmch drives ha[31:3]# during snoop cycles on behalf of primary pci. note that the address bus is inverted on the processor bus. hd[63:0]# i/o agtl+ host data: these signals are connected to the processor data bus. note that the data signals are inverted on the processor bus. ads# i/o agtl+ address strobe: the processor bus owner asserts ads# to indicate the first of two cycles of a request phase . bnr# i/o agtl+ block next request: used to block the current request bus owner from issuing a new request. this signal is used to dynamically control the processor bus pipeline depth. bpri# o agtl+ priority agent bus request: the gmch is the only priority agent on the processor bus. it asserts this signal to obtain the ownership of the address bus. this signal has priority over symmetric bus requests and causes the current symmetric owner to stop issuing new transactions, unless the hlock# signal was asserted. dbsy# i/o agtl+ data bus busy: used by the data bus owner to hold the data bus for transfers requiring more than one cycle. defer# o agtl+ defer: the gmch generates a deferred response as defined by the rules of the gmch dynamic defer policy. the gmch also uses the defer# signal to indicate a processor retry response. drdy# i/o agtl+ data ready: asserted for each cycle that data is transferred. hit# i/o agtl+ hit: indicates that a caching agent holds an unmodified version of the requested line. also driven in conjunction with hitm# by the target to extend the snoop window. hitm# i/o agtl+ hit modified: indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line. hitm# is also driven in conjunction with hit# to extend the snoop window. hlock# i agtl+ host lock: all processor bus cycles sampled with the assertion of hlock# and ads#, until the negation of hlock# must be atomic (i.e., no hub interface or gmch graphics snoopable access to dram is allowed when hlock# is asserted by the processor). hreq[4:0]# i/o agtl+ host request command: asserted during both clocks of r equest phase. in the first clock, the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. in the second clock, the signals carry additional information to define the complete transaction type. the transactions supported by the gmch are defined in the host interface section of this document.
r intel ? 82810/82810-dc100 (gmch) datasheet 21 signal name type description htrdy# i/o agtl+ host target ready: indicates that the target of the processor transaction is able to enter the data transfer phase. rs[2:0]# i/o agtl+ response signals: indicates type of response as shown below: rs[2:0] response type 000 idle state 001 retry response 010 deferred response 011 reserved (not driven by the gmch) 100 hard failure (not driven by the gmch) 101 no data response 110 implicit writeback 111 normal data response 2.2. system memory interface signals signal name type description smaa[11:0] smab[7:4]# sbs[1:0] o cmos memory address: smaa[11:0] and smab[7:4]# are used to provide the multiplexed row and column address to dram. sbs[1:0] provide the bank select. smd[63:0] i/o cmos memory data: these signals are used to interface to the dram data bus. sdqm[7:0] o cmos input/output data mask: these pins act as synchronized output enables during read cycles and as a byte enables during write cycles. scs[3:0]# o cmos chip select: for the memory row configured with sdram, these pins perform the function of selecting the particular sdram components during the active state. sras# o cmos sdram row address strobe: these signals drive the sdram array directly without any external buffers. scas# o cmos sdram column address strobe: these signals drive the sdram array directly without any external buffers. swe# o cmos write enable signal: swe# is asserted during writes to dram. scke[1:0] o cmos system memory clock enable: scke sdram clock enable is used to signal a self-refresh or power-down command to an sdram array when entering system sus pend.
intel ? 82810/82810-dc100 (gmch) r 22 datasheet 2.3. display cache interface signals (82810-dc100 only) signal name type description lcs# o cmos chip select: for the memory row configured with sdram, these pins perform the function of selecting the particular sdram components during the active state. ldqm[3:0] o cmos input/output data mask: these pins control the memory array and act as synchronized output enables during read cycles and as a byte enables during write cycles. lsras# o cmos sdram row address strobe: the lsras# signal is used to generate sdram command encoded on lsras#/lscas#/lwe# signals. when lras# is sampled active at the rising edge of the sdram clock, the row address is latched into the sdrams. lscas# o cmos sdram column address strobe: the lscas# signal is used to generate sdram command encoded on lsras#/lscas#/lwe# signals. when lscas# is sampled active at the rising edge of the sdram clock, the column address is latched into the sdrams. lma[11:0] o cmos memory address: lma[11:0] is used to provide the multiplexed row and column address to dram. lwe# o cmos write enable signal: lwe# is asserted during writes to dram. lmd[31:0] i/o cmos memory data: these signals are used to interface to the dram data bus of dram array. 2.4. hub interface signals signal name type description hl[10:0] i/o hub interface signals: signals used for the hub interface. hlstrb i/o packet strobe: one of two differential strobe signals used to transmit or receive packet data. hlstrb# i/o packet strobe compliment: one of two differential strobe signals used to transmit or receive packet data. hubref i ref hub reference: sets the differential voltage reference for the hub interface. hcomp i/o hub compensation pad: used to calibrate the hub interface buffers.
r intel ? 82810/82810-dc100 (gmch) datasheet 23 2.5. display interface signals signal name type description vsync o 3.3v crt vertical synchronization: this signal is used as the vertical sync (polarity is programmable) or vsync interval. hsync o 3.3v crt horizontal synchronization: this signal is used as the horizontal sync (polarity is programmable) or hsync interval. iwaste i ref waste reference: this signal must be tied to ground. iref i ref set pointer resistor for the internal color palette dac: a 174 ohm 1% resistor is recommended red o analog crt analog video output from the internal color palette dac: the dac is designed for a 37.5 ohms equivalent load on each pin (e.g. 75 ohms resistor on the board, in parallel with the 75 ohms crt load) green o analog crt analog video output from the internal color palette dac: the dac is designed for a 37.5 ohms equivalent load on each pin (e.g. 75 ohms resistor on the board, in parallel with the 75 ohms crt load) blue o analog crt analog video output from the internal color palette dac: the dac is designed for a 37.5 ohms equivalent load on each pin (e.g., 75 ohms resistor on the board, in parallel with the 75 ohms crt load) ddcscl i/od cmos crt monitor ddc interface clock: (also referred to as vesa tm display data channel, also referred to as the monitor plug-n-play interface.) for ddc1, ddcscl and ddcsda provides a unidirectional channel for extended display id. for ddc2, ddcscl and ddcsda it can be used to establish a bi-directional channel based on i 2 c protocol. the host can request extended display id or video display interface information over the ddc2 channel. ddcsda i/od cmos crt monitor ddc interface data:
intel ? 82810/82810-dc100 (gmch) r 24 datasheet 2.6. digital video output signals/tv-out pins signal name type description tvclkin/int# i 1.8v low voltage tv clock in (tv-out mode): in 1.8v tv-out usage, the tvclkin pin functions as a pixel clock input to the gmch from the tv encoder. the tvclkin frequency ranges from 20 mhz to 40 mhz depending on the mode (e.g., ntsc or pal) and the overscan compensation values in the tv encoder. clkin has a worse case duty cycle of 60%/40% coming in to the gmch. flat panel interrupt (lcd mode): in flat panel usage, the int# pin is asserted to cause an interrupt (typically, to indicate a hot plug or unplug of a flat panel). in flat panel usage, this pin is connected internally to a pull- up resistor. clkout[1:0] o 1.8v lcd/tv port clock out: these pins provide a differential pair reference clock that can run up to 85 mhz. blank# o 1.8v flicker blank or border period indication: blank# is a programmable output pin driven by the graphics control. when programmed as a blank period indication, this pin indicates active pixels excluding the border. when programmed as a border period indication, this pin indicates active pixel including the border pixels. ltvdata[11:0] o 1.8v lcd/tv data: these signals are used to interface to the lcd/tv-out data bus. tvvsync o 1.8v vertical sync: vsync signal for the ltv interface. the active polarity of the signal is programmable. tvhsync o 1.8v horizontal sync: hsync signal for the ltv interface. the active polarity of the signal is programmable. ltvcl i/od cmos lcd/tv clock: clock pin for 2-wire interface. ltvda i/od cmos lcd/tv data: data pin for 2-wire interface.
r intel ? 82810/82810-dc100 (gmch) datasheet 25 2.7. power signals signal name type description v_1.8 power core power (1.8v) v_3.3 power i/o buffer power (3.3v) vsus_3.3 power system memory buffer power (separate 3.3v power plane for power down modes) vccda power display power signal (connect to an isolated 1.8v plane with vccdaca1 and vccdaca2) vccdaca1 power display power signal (connect to an isolated 1.8v plane with vccda and vccdaca2) vccha power isolated 1.8v power vccba power isolated 1.8v power vccdaca2 power display power signal (connect to an isolated 1.8v plane with vccda and vccdaca1) vssda power display ground signal vssdaca power display ground signal vss power core ground 2.8. clock signals signal name type description hclk i cmos host clock input: clock used on the host interface. externally generated 66/100 mhz clock. sclk i cmos system memory clock: clock used on the output buffers of system memory. externally generated 100 mhz clock. ltclk o cmos transmit clock: ltclk is an internally generated local memory clock used to clock the input buffers of the sdram devices of the display cache. loclk o cmos output clock: loclk is an internally generated clock used to drive lrclk. lrclk i cmos receive clock: lrclk is a display cache clock used to clock the input buffers of the gmch. dclkref i cmos display interface clock: dclkref is a 48 mhz clock generated by an external clock synthesizer to the gmch. hlclk i cmos hub interface clock: 66 mhz hub interface clock generated by an external clock synthesizer.
intel ? 82810/82810-dc100 (gmch) r 26 datasheet 2.9. miscellaneous interface signals signal name type description gtlrefa i ref agtl reference voltage: reference signal to the host interface. gtlrefb i ref agtl reference voltage: reference signal to the host interface. reset# i global reset: driven by the ich/ich0 when pcirst# is active. 2.10. power-up/reset strap options (82810) table 1 lists power-up options that are loaded into the 82810 gmch during cold reset. table 1. power-up options (82810) pin location description f22 xor chain test select: set to 0 for normal operation. it must be set to 1 to enter xor tree mode during reset. this pin must remain 1 during the entire xor tree test. f21 all z select: if the pin is set to 1, all signals are tri-stated during reset. for normal operation, this pin should be set to 0. g23 host frequency select: if this pin is set to 0 during reset, the host bus frequency is 66 mhz. if the pin is set to 1, the host bus frequency is 100 mhz. g22 in-order queue depth status: if set to 0 during reset, the ioqd is 4. if set to 1, the ioqd is 1. 2.11. power-up/reset strap options (82810-dc100) table 2 list power-up options that are loaded into the 82810-dc100 gmch during cold reset. table 2. power-up options (82810-dc100) signal description lmd[31] xor chain test select: lmd[31] is set to 0 for normal operation. it must be set to 1 to enter xor tree mode during reset. this signal must remain 1 during the entire xor tree test. lmd[30] all z select: if lmd[30] is set to 1, all signals are tri-stated during reset. for normal operation, lmd[30] should be set to 0 lmd[29] host frequency select: if lmd[29] is set to 0 during reset, the host bus frequency is 66 mhz. if lmd[29] is set to 1, the host bus frequency is 100 mhz. lmd[28] in-order queue depth status: the value on lmd[28] sampled at the rising edge of cpurst# reflects if the ioqd is set to 1 or 4. if lmd[28] is set to 0, the ioqd is 4. if lmd[28] is set to 1, the ioqd is 1.
r intel ? 82810/82810-dc100 (gmch) datasheet 27 3. configuration registers this section describes the following register sets: pci configuration registers (82810 and 82810-dc100). the gmch contains pci configuration registers for device 0 (host-hub interface bridge/dram controller) and device 1 (gmch internal graphics device). display cache interface registers (82810-dc100 only). this register set is used for configuration of the display cache (dc) interface. the registers are located in memory space. the memory space addresses listed are offsets from the base memory address programmed into the mmadr register (device 1, pci configuration offset 14h). display cache detect and diagnostic registers (82810-dc100 only). this register set can be used for dc memory detection and testing. these registers are accessed via either i/o space or memory space. the memory space addresses listed are offsets from the base memory address programmed into the mmadr register (device 1, pci configuration offset 14h). note that the gmch also contains an extensive set of registers and instructions for controlling its graphics operations. intel graphics drivers provide the software interface at this architectural level. the register/instruction interface is transparent at the application programmers interface (api) level and thus, beyond the scope of this document. 3.1. register nomenclature and access attributes ro read only. if a register is read only, writes to this register have no effect. r/w read/write. a register with this attribute can be read and written r/wc read/write clear. a register bit with this attribute can be read and written. however, a write of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect. r/wo read/write once. a register bit with this attribute can be written to only once after power up. after the first write, the bit becomes read only. reserved bits some of the gmch registers described in this section contain reserved bits. these bits are labeled "reserved or intel reserved. software must deal correctly with fields that are reserved. on reads, software must use appropriate ma sks to extract the defi ned bits and not rely on reserved bits being any particular value. on writes, software must ensure that the values of reserved bit positions are preserved. that is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. note the software does not need to perform read, merge, write operation for the configuration address register. reserved registers in addition to reserved bits within a register, the gmch contains address locations in the configuration space of the host-hub interface bridge/dram controller and the internal graphics device entities that are marked either "reserved or intel reserved. when a reserved register location is read, a random value can be returned. (reserved registers can be 8-, 16-, or 32-bit in size). registers that are marked as reserved must not be modified by system software. writes to reserved registers may cause system failure. default value upon reset upon a full reset, the gmch sets all of its internal configuration registers to predetermined default states. some register values at reset are determined by external strapping options. the default state represents the minimum functionality feature set required to successfully bring up the system. hence, it does not represent the optimal system configuration. it is the res ponsibility of the system initialization software (usually bios) to pr operly determine the dram configurations, operating parameters and optional system features that are applicable, and to program the gmch registers accordingly.
intel ? 82810/82810-dc100 (gmch) r 28 datasheet 3.2. pci configuration space access the gmch and the ich are physically connected via the hub interface. from a configuration standpoint, the hub interface connecting the gmch and the ich is logically pci bus #0 . all devices internal to the gmch and ich appear to be on pci bus #0. the system primary pci expansion bus is physically attached to the ich and, from a configuration standpoint, appears as a hierarchical pci bus behind a pci-to-pci bridge. the primary pci expansion bus connected to the ich has a programmable pci bus number. note: even though the primary pci bus is referred to as pci0 in this document it is not pci bus #0 from a configuration standpoint. the gmch contains two pci devices within a single physical component. the configuration registers for both device 0 and 1 are mapped as devices residing on pci bus #0. device 0: host-hub interface bridge/dram controller. logically this appears as a pci device residing on pci bus #0. physically device 0 contains the pci registers, dram registers, and other gmch specific registers. device 1: gmch internal graphics device. these registers contain the pci registers for the gmch internal graphics device. note that a physical pci bus #0 does not exist. the hub interface and the internal devices in the gmch and ich logically constitute pci bus #0 to configuration software. 3.2.1. pci bus configuration mechanism the pci bus defines a slot based "configuration space" that allows each device to contain up to 8 functions with each function containing up to 256 8-bit configuration registers. the pci specification defines two bus cycles to access the pci configuration space: configuration read and configuration write. memory and i/o spaces are supported directly by the processor. configuration space is supported by a mapping mechanism implemented within the gmch. the pci specification defines two mechanisms to access configuration space, mechanism #1 and mechanism #2. the gmch supports only mechanism #1 the configuration access mechanism makes use of the config_address register and config_data register. to reference a configuration register a dword i/o write cycle is used to place a value into config_address that specifies the pci bus, the device on that bus, the function within the device, and a specific configuration register of the device function being accessed. config_address[31] must be 1 to enable a configuration cycle. config_data then becomes a window into the four bytes of configuration space specified by the contents of config_address. any read or write to config_data results in the gmch translating the config_address into the appropriate configuration cycle. the gmch is responsible for translating and routing the processor i/o accesses to the config_address and config_data registers to internal gmch configuration registers, the internal graphic device, or the hub interface.
r intel ? 82810/82810-dc100 (gmch) datasheet 29 3.2.2. logical pci bus #0 configuration mechanism the gmch decodes the bus number (bits 23:16) and the device number fields of the config_address register. if the bus number field of config_address is 0 the configuration cycle is targeting a pci bus #0 device. device #0: the host-hub interface bridge/dram controller entity within the gmch is hardwired as device #0 on pci bus #0. device #1: the internal graphics device entity within the gmch is hardwired as device #1 on pci bus #0. configuration cycles to one of the gmch internal devices are confined to the gmch and not sent over the hub interface. note: accesses to devices #2 to #31 on pci bus #0 are forwarded over the hub interface. 3.2.3. primary pci (pci0) and downstream configuration mechanism if the bus number in the config_address is non-zero the gmch generates a configuration cycle over the hub interface. the ich compares the non-zero bus number with the secondary bus number and subordinate bus number registers of its p2p bridges to determine if the configuration cycle is meant for primary pci (pci0), or a downstream pci bus. 3.2.4. internal graphics device configuration mechanism from the chipset configuration perspective the internal graphics device is seen as a pci device (device #1) on pci bus #0. configuration cycles that target device #1 on pci bus #0 are claimed by the internal graphics device and are not forwarded via hub interface to the ich. 3.2.5. gmch register introduction the gmch contains two sets of software accessible registers, accessed via the host i/o address space: control registers i/o mapped into the host i/o space. these registers control access to pci configuration space (see section entitled i/o mapped registers) internal configuration registers residing within the gmch are partitioned into two logical device register sets (logical since they reside within a single physical device). the first register set is dedicated to host-hub interface bridge/dram controller functionality (controls pci0 such as dram configuration, other chip-set operating parameters and optional features). the second register block is dedicated to the internal graphics device in the gmch. the gmch supports pci configuration space accesses using the mechanism denoted as configuration mechanism #1 in the pci specification. the gmch internal registers (both i/o mapped and configuration registers) are accessible by the host. the registers can be accessed as byte, word (16-bit), or dword (32-bit) quantities, with the exception of config_address that can only be accessed as a dword. all multi-byte numeric fields use "little- endian" ordering (i.e., lower addresses contain the least significant parts of the field).
intel ? 82810/82810-dc100 (gmch) r 30 datasheet 3.3. i/o mapped registers gmch contains two registers that reside in the processor i/o address space - the configuration address (config_address) register and the configuration data (config_data) register. the configuration address register enables/disables the configuration space and determines what portion of configuration space is visible through the configuration data window. 3.3.1. config_address ? configuration address register i/o address: 0cf8h accessed as a dword default value: 00000000h access: read/write size: 32 bits config_address is a 32 bit register accessed only when referenced as a dword. a byte or word reference will "pass through" the configuration address register and the hub interface onto the pci #0 bus as an i/o cycle. the config_address register contains the bus number, device number, function number, and register number for which a subsequent configuration access is intended. 31 30 24 23 16 config en reserved (0) bus number 15 11 10 8 7 2 1 0 device number function number register number reserved bit descriptions 31 configuration enable (cfge). 1 = enable accesses to pci configuration space 0 = disable accesses to pci configuration space 30:24 reserved (these bits are read only and have a value of 0). 23:16 bus number. when the bus number is programmed to 00h the target of the configuration cycle is either a hub interface agent gmch or the ich. the configuration cycle is forwarded to the hub interface if the bus number is programmed to 00h and the gmch is not the target. 15:11 device number. this field selects one agent on the pci bus selected by the bus number. when the bus number field is 00 the gmch decodes the device number field. the gmch is always device number 0 for the host-hub interface bridge/dram controller entity and device number 1 for the internal graphics device. therefore, when the bus number =0 and the device number=0 or 1 the internal gmch devices are selected. for bus numbers resulting in the hub interface configuration cycles the gmch pr opagates the device number field as ha[15:11]. 10:8 function number. this field is mapped to ha[10:8] during the hub interface configuration cycles. this allows the configuration registers of a particular function in a multi-function device to be accessed. the gmch ignores configuration cycles to its two internal devices if the function number is not equal to 0.
r intel ? 82810/82810-dc100 (gmch) datasheet 31 bit descriptions 7:2 register number. this field selects one register within a particular bus, device, and function as specified by the other fields in the configuration address register. this field is mapped to ha[7:2] during the hub interface configuration cycles. 1:0 reserved. 3.3.2. config_data ? configuration data register i/o address: 0cfch default value: 00000000h access: read/write size: 32 bits config_data is a 32 bit read/write window into configuration space. the portion of configuration space that is referenced by config_data is determined by the contents of config_address. bit descriptions 31:0 configuration data window (cdw). if bit 31 of config_address is 1, any i/o reference that falls in the config_data i/o space will be mapped to configuration space using the contents of config_address. 3.4. host-hub interface bridge/dram controller device registers (device 0) table 3 shows the gmch configuration space for device #0.
intel ? 82810/82810-dc100 (gmch) r 32 datasheet table 3. gmch pci configuration space (device 0) address offset register symbol register name default value access 00C01h vid vendor identification 8086h ro 02C03h did device identification 7120h/7122h ro 04C05h pcicmd pci command register 0006h r/w 06C07h pcists pci status register 0080h ro, r/wc 08h rid revision identification 00h ro 09h ? reserved 00h ? 0ah subc sub-class code 00h ro 0bh bcc base class code 06h ro 0ch ? reserved 00h ? 0dh mlt master latency timer 00h ro 0eh hdr header type 00h ro 0fh ? reserved ? ? 10?2bh ? reserved ? ? 2c?2dh svid subsystem v endor identification 0000h r/wo 2e?2fh sid subsystem i dentification 0000h r/wo 30?33h ? reserved ? ? 34h capptr capabilities pointer 00h ro 35?4fh ? reserved ? ? 50h gmchcfg gmch configuration 60h r/w 51h pam programmable attributes 00h r/w 52h drp dram row population 00h r/w 53h dramt dram timing register 08h r/w 54?57h ? reserved ? ? 58h fdhc fixed dram hole control 00h r/w 58?6fh ? reserved ? ? 70h smram system management ram control 00h r/w 72?73h missc miscellaneous control 0000h r/w 74?7fh ? reserved ? ? 80h missc2 miscellaneous control 2 00h r/w 81?91h ? reserved ? ? 92?93h bsc buffer strength control ffffh r/w 94?ffh ? reserved ? ?
r intel ? 82810/82810-dc100 (gmch) datasheet 33 3.4.1. vid ? vendor identification register (device 0) address offset: 00C01h default value: 8086h attribute: read only size: 16 bits the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identify any pci device. writes to this register have no effect. bit description 15:0 vendor identification number. this is a 16-bit value assigned to intel. intel vid = 8086h. 3.4.2. did ? device identification register (device 0) address offset: 02C03h default value: 82810 = 7120h 82810-dc100 = 7122h attribute: read only size: 16 bits this 16-bit register combined with the vendor identification register uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 device identification number. this is a 16 bit value assigned to the gmch host-hub interface bridge/dram controller device #0. 3.4.3. pcicmd ? pci command register (device 0) address offset: 04C05h default: 0006h access: read/write size 16 bits this 16-bit register provides basic control over the gmch pci0 (i.e., hub-interface) interfaces ability to respond to hub interface cycles.
intel ? 82810/82810-dc100 (gmch) r 34 datasheet 15 10 9 8 reserved (0) fb2b (not impl) serr en 76543210 addr/data steppin g (not impl) parity error en (not impl) vga pal sn (not impl) mem wr & inval en (not impl) special cycle en (not impl) bus master en (not impl) mem accen (not impl) i/o accen (not impl) bit descriptions 15:10 reserved. 9 fast back-to-back. (not implemented; hardwired to 0). writes to this bit position have no effect 8 serr enable (serre). this bit is a global enable bit for device #0 serr messaging. the gmch does not have an serr# signal. the gmch communicates the serr condition by sending an serr message to the ich. if this bit is set to a 1, the gmch is enabled to generate serr messages over the hub interface for specific device #0 error conditions (note: the only serr condition for the gmch is received target abort, therefore there are no other serr enable bits in the gmch ). if serre is reset to 0, then the serr message is not generated by the gmch for device #0. note: this bit only controls serr messaging for the device #0. 7 address/data stepping. (not implemented; hardwired to 0). writes to this bit position have no effect. 6 parity error enable (perre). (not implemented; hardwired to 0). writes to this bit position have no effect. 5 vga palette snoop. (not implemented, hardwired to 0). writes to this bit position have no effect 4 memory write and invalidate enable. (not implemented; hardwired to 0). writes to this bit position have no effect 3 special cycle enable. (not implemented; hardwired to 0). writes to this bit position have no effect 2 bus master enable (bme). (not implemented: hardwired to 1). gmch is always a bus master. writes to this bit position have no effect. 1 memory access enable (mae). (not implemented; hardwired to 1). writes to this bit position have no effect 0 i/o access enable (ioae). (not implemented by the gmch: hardwired to 0). writes to this bit position have no effect
r intel ? 82810/82810-dc100 (gmch) datasheet 35 3.4.4. pcists ? pci status register (device 0) address offset: 06C07h default value: 0080h access: read only, read/write clear size: 16 bits pcists is a 16 bit status register that reports the occurrence of error events on the hub interface. 15 14 13 12 11 10 9 8 detected par error (hw=0) sig sys error recog mast abort sta rec target abort sta (hw=0) sig target abort sta (hw=0) devsel# timing (hw=00) data par detected (hw=0) 76 543 0 fb2b (hw=1) reserved cap list (hw=0) reserved bit descriptions 15 detected parity error (dpe) ro. this bit is hardwired to 0. writes to this bit position have no effect. 14 signaled system error (sse)rwc. this bit is set to 1 when the gmch device #0 generates an serr message over hub interface for any enabled device #0 error condition. device #0 error conditions are enabled in the pcicmd register. device #0 error flags are read/reset from the pcists register. software sets sse to 0 by writing a 1 to this bit. (note: the only serr condition for gmch is received target abort, therefore there are no other serr enable bits in the gmch ). 13 received master abort status (rmas) rwc. this bit is set when the gmch generates a hub- interface request that receives a master abort completion packet. software clears this bit by writing a 1 to it. 12 received target abort status (rtas) rwc. this bit is set when the gmch generates a hub interface request that receives a target abort completion packet. software clears this bit by writing a 1 to it. 11 signaled target abort status (stas) ro. (not implemented; hardwired to a 0). writes to this bit position have no effect. 10:9 devsel# timing (devt) ro. these bits are hardwired to 00. writes to these bit positions have no effect. device #0 does not physically connect to pci0. these bits are set to 00 (fast decode) so that optimum devsel timing for pci0 is not limited by the gmch. 8 data parity detected (dpd) ro. this bit is hardwired to a 0. writes to this bit position have no effect. 7 fast back-to-back (fb2b) ro. this bit is hardwired to 1. writes to these bit positions have no effect. device #0 does not physically connect to pci. this bit is set to 1 (indicating fast back-to-back capability) so that the optimum setting for pci is not limited by the gmch. 6:5 reserved. 4 capability list (clist)ro. this bit is hardwired to 0, to indicate to the configuration software that this device/function does not implement a new list of features, and that there is no capptr. 3:0 reserved.
intel ? 82810/82810-dc100 (gmch) r 36 datasheet 3.4.5. rid ? revision identification register (device 0) address offset: 08h default value: 02h access: read only size: 8 bits this register contains the revision number of the gmch device 0. these bits are read only and writes to this register have no effect. bit description 7:0 revision identification number. this is an 8-bit value that indicates the revision identification number for the gmch device #0. for the a-2 stepping, this value is 02h. 3.4.6. subc ? sub-class code register (device 0) address offset: 0ah default value: 00h access: read only size: 8 bits this register contains the sub-class code for the gmch device #0. this code is 00h indicating a host bridge device. the register is read only. bit description 7:0 sub-class code (subc). this is an 8-bit value that indicates the category of bridge into which the gmch falls. the code is 00h indicating a host bridge. 3.4.7. bcc ? base class code register (device 0) address offset: 0bh default value: 06h access: read only size: 8 bits this register contains the base class code of the gmch device #0. this code is 06h indicating a bridge device. this register is read only. bit description 7:0 base class code (basec). this is an 8-bit value that indicates the base class code for the gmch. this code has the value 06h, indicating a bridge device.
r intel ? 82810/82810-dc100 (gmch) datasheet 37 3.4.8. mlt ? master latency timer register (device 0) address offset: 0dh default value: 00h access: read only size: 8 bits mlt function has moved to the ich/ich0, therefore this register is not implemented in the gmch. bit descriptions 7:0 master latency timer value. this read only field always returns 0s. 3.4.9. hdr ? header type register (device 0) offset: 0eh default: 00h access: read only size: 8 bits this register identifies the header layout of the configuration space. no physical register exists at this location. bit descriptions 7:0 header type. this read only field always returns 0s. 3.4.10. svid ? subsystem vendor identification register (device 0) offset: 2cC2dh default: 0000h access: read/write once size: 16 bits bit description 15:0 subsystem vendor idr/wo. this value is used to identify the vendor of the sub system. this field should be programmed by bios during boot-up. once written, this register becomes read only. this register can only be cleared by a reset.
intel ? 82810/82810-dc100 (gmch) r 38 datasheet 3.4.11. sid ? subsystem identification register (device 0) offset: 2eC2fh default: 0000h access: read/write once size: 16 bits bit description 15:0 subsystem idr/wo. this value is used to identify a particular sub system. this field s hould be programmed by bios during boot-up. once written, this register becomes read only. this register can only be cleared by a reset. 3.4.12. capptr ? capabilities pointer (device 0) offset: 34h default: 00h access: read only size: 8 bits the capptr provides the offset that is the pointer to the location where the agp registers are located. bit description 7:0 pointer to the start of agp register block. since there is no agp bus on the gmch, this field is set to 00h.
r intel ? 82810/82810-dc100 (gmch) datasheet 39 3.4.13. gmchcfg ? gmch configuration register (device 0) offset: 50h default: 60h access: read/write, read only size: 8 bits 765 43210 reserved processor latency timer reserved dram pg closing policy reserved d8 hole enable cd hole enable bit description 7 reserved 6 processor latency timer (clt). 1 = a deferrable processor cycle is only deferred after it has been held in a snoop stall for 31 clocks and another ads# has arrived. 0 = a deferrable processor cycle is deferred immediately after the gmch receives another ads# 5:4 reserved 3 dram page closing policy (dpcp). this bit controls whether the gmch will precharge bank or precharge all during the service of a page miss. 1 = the gmch prechanges all during the service of a page miss. 0 = the gmch prechanges bank during the service of a page miss. 2 reserved 1 d8 hole enable (d8hen). 1 = enable. all accesses to the address range 000d8000hC000dfffh are forwarded on to the ich, independent of the programming of the pam registers. 0 = disable. the d8 hole region is controlled by bits 3:2 of the pam registers. 0 cd hole enable ( cdhen ). 1 = enable. all accesses to the address range 000dc000hC000dffffh are forwarded on to ich, independent of the programming of the pam register. 0 = disable. the cd hole region is controlled by bits 3 & 2 of the pam register.
intel ? 82810/82810-dc100 (gmch) r 40 datasheet 3.4.14. pamrprogrammable attributes register (device 0) address offset: 51h default value: 00h access: read/write size: 8 bits the programmable attributes register controls accesses to the memory range 000c0000h to 000fffffh. 76543210 seg_f access control seg_e access control seg_d access control seg_c access control bit description 7:6 seg_f access control. this field controls accesses to 000f0000 to 000fffff. 00 = disabled, all accesses are forwarded to the ich 01 = read only, reads are directed to system memory dram and writes are forwarded to the ich 10 = write only, writes are directed to system memory dram and reads are forwarded to the ich 11 = read/write, all accesses are directed to system memory dram. 5:4 seg_e access control. this field controls accesses to 000e0000 to 000effff. 00 = disabled, all accesses are forwarded to the ich 01 = read only, reads are directed to system memory dram and writes are forwarded to the ich 10 = write only, writes are directed to system memory dram and reads are forwarded to the ich 11 = read/write, all accesses are directed to system memory dram. 3:2 seg_d access control. this field controls accesses to 000d0000 to 000dffff. 00 = disabled, all accesses are forwarded to the ich 01 = read only, reads are directed to system memory dram and writes are forwarded to the ich 10 = write only, writes are directed to system memory dram and reads are forwarded to the ich 11 = read/write, all accesses are directed to system memory dram. 1:0 seg_c access control. this field controls accesses to 000c0000 to 000cffff. 00 = disabled, all accesses are forwarded to the ich 01 = read only, reads are directed to system memory and writes are forwarded to the ich 10 = write only, writes are directed to system memory and reads are forwarded to the ich 11 = read/write, all accesses are directed to system memory.
r intel ? 82810/82810-dc100 (gmch) datasheet 41 cd hole (dc000h C dffffh) this 16 kb area is controlled by 2 sets of attribute bits. host-initiated cycles in this region are forwarded to the ich based upon the programming of pam[3:2] and the cdhen bit in the gmchcfg register. video buffer area (a0000h C bffffh) this 128 kb area is not controlled by attribute bits. the host-initiated cycles in this region are always forwarded to either the graphics device or to the ich unless this range is accessed in smm mode. routing of these accesses is controlled by the graphics mode select field of the smram register. this area can be programmed as smm area via the smram register. this range can not be accessed from the hub interface. 3.4.15. drp ? dram row population register (device 0) address offset: 52h default value: 00h access: read/write (read only) size: 8 bits gmch supports 4 physical rows of system memory in 2 dimms. the width of a row is 64 bits. the dram row population register defines the population of each side of each dimm. note: this entire register becomes read only when the smm space locked ( d_lck) bit is set in the smram ? system management ram control register (offset 70h). 15 4 3 0 dimm 1 population dimm 0 population bit description 7:4 dimm 1 population. this field indicates the population of dimm 1. (see table below ) 3:0 dimm 0 population. this field indicates the population of dimm 0. (see table below )
intel ? 82810/82810-dc100 (gmch) r 42 datasheet table 4. programming dram row population register fields field value (hex) size technology population population 0 0 mb empty empty 1 8 mb 16mb 4x(1mx16) empty 3 16 mb 16mb 4x(1mx16) 4x(1mx16) 4 16 mb 16mb 8x(2mx8) empty 5 24 mb 16mb 8x(2mx8) 4x(1mx16) 6 32 mb 16mb 8x(2mx8) 8x(2mx8) 7 32 mb 64mb 4x(4mx16) empty 7 32 mb 128mb 2x(4mx32) empty 8 48 mb mixed 4x(4mx16) 8x(2mx8) 8 48 mb 64mb 4x(4mx16) 2x(2mx32) 8 48 mb mixed 2x(4mx32) 2x(2mx32) 9 64 mb 64mb 4x(4mx16) 4x(4mx16) 9 64 mb 128mb 2x(4mx32) 2x(4mx32) a 64 mb 64mb 8x(8mx8) empty a 64 mb 128mb 4x(8mx16) empty b 96 mb 64mb 8x(8mx8) 4x(4mx16) b 96 mb 128mb 4x(8mx16) 2x(4mx32) b 96 mb mixed 4x(8mx16) 4x(4mx16) c 128 mb 64mb 8x(8mx8) 8x(8mx8) c 128 mb 128mb 4x(8mx16) 4x(8mx16) d 128 mb 128mb 8x(16mx8) empty e 192 mb 128mb 8x(16mx8) 4x(8mx16) e 192 mb mixed 8x(16mx8) 8x(8mx8) f 256 mb 128mb 8x(16mx8) 8x(16mx8)
r intel ? 82810/82810-dc100 (gmch) datasheet 43 3.4.16. dramt ? dram timing register (device 0) address offset: 53h default value: 08h access: read/write size: 8 bits the dramt register controls the operating mode and the timing of the dram controller. 7 543210 sdram mode select dram cycle time intel reserved cas# latency sdram ras# to cas# dly sdram ras# precharge bit description 7:5 sdram mode select (sms). these bits select the operational mode of the gmch dram interface. the special modes are intended for initialization at power up. sms mode 000 dram in self-refresh mode, refresh disabled (default) 001 normal operation, refresh 15.6usec 010 normal operation, refresh 7.8usec 011 reserved nop command enabled. in this mode all processor cyscles to sdram result in a nop command on sdram interface. all bank precharge enable. in this mode processor cycles to sdram result in an all bank precharge command on the sdram interface. mode register set enable. in this mode all processor cycles to sdram result in a m ode register set command on the sdram interface. the command is driven on the smaa[11:0] and the sbs[0] lines. smaa[2:0] must always be driven to 010 for burst of 4 mode. smaa[3] must be driven to 1 for interleave wrap type. smaa[4] needs to be driven to the value programmed in the cas# latency bit. smaa[6:5] should always be driven to 01. smaa[11:7] and sbs[0] must be driven to 000000. bios must calculate and drive the correct host address for each row of memory such that the correct command is driven on the smaa[11:0] and sbs[0] lines. cbr enable. in this mode all processor cycles to sdram result in a cbr cycle on the sdram interface. note: bios must take into consideration smab inversion when programming dimm 2. 4 dram cycle time ( dct ). this bit controls the number of sclks for an access cycle. bit4 tras trc 0 5 sclks 7 sclks (default) 1 6 sclks 8 sclks 3 intel reserved.
intel ? 82810/82810-dc100 (gmch) r 44 datasheet bit description 2 cas# latency (cl). this bit controls the number of clks between when a read command is sampled by the sdrams and when the gmch samples read data from the sdrams. 0 = 3 sclks (default) 1 = 2 sclks 1 sdram ras# to cas# delay (srcd). this bit controls the number of sclks from a row activate command to a read or write command. 0 = 3 sclks (default) 1 = 2 sclks 0 sdram ras# precharge (srp). this bit controls the number of sclks for ras# precharge. 0 = 3 sclks (default) 1 = 2 sclks 3.4.17. fchc ? fixed dram hole control register (device 0) offset: 58h default: 00h access: read/write size: 8 bits this 8-bit register controls 1 fixed dram holes: 15C16mb. 76 0 hole enable reserved bit description 7 hole enable (hen)rw. this bit enables a memory hole in dram space. host cycles matching a enabled hole are passed on to the ich/ich0 through the hub interface. hub interface cycles matching an enabled hole are ignored by the gmch. note that the hole is not re-mapped 0 = disabled (default) 1 = enabled (15mbC16mb; 1mb size) 6:0 reserved
r intel ? 82810/82810-dc100 (gmch) datasheet 45 3.4.18. smram ? system management ram control register (device 0) address offset: 70h default value: 00h access: read/write size: 8 bits the smram register controls how accesses to compatible and extended smram spaces are treated, and how much (if any) memory used from the system to support both smram and graphics local memory needs. 76543210 graphics mode select upper smm select lower smm select smm space locked e_smra m_err bit description 7:6 graphics mode select (gms). this field is used to enable/disable the internal graphics device and select the amount of system memory that is used to s upport the internal graphics device. 00 = graphics device disabled, no memory used (device 1 is not accessible in this case) 01 = reserved 10 = graphics device enabled, 512 kb of memory used 11 = graphics device enabled 1 mb of memory used note: when the graphics device is disabled (00) the graphics device and all of its memory and i/o functions are disabled and the clo cks to this logic are tur ned off, memory accesses to the vga range. the 512 kb and 1 mb space selected by this field is used by video bios for handling support of vga when no gmch graphics driver is present (e.g., a dos boot). (a0000hCbffffh) are forwarded to the hub interface, and no system memory is used to s upport the internal graphics device. when this field is non-zero, the graphics device of the gmch and all of its memory and i/o functions are enabled, all non-smm memory accesses to the vga range are handled internally and the selected amount of system memory (0, 512 kb or 1 mb) is used from system memory to support the internal graphics device. once d_lck is set, these bits becomes read only.
intel ? 82810/82810-dc100 (gmch) r 46 datasheet bit description 5:4 upper smm select ( usmm ). this field is used to enable/disable the various smm memory ranges above 1meg. tseg is a block of memory (used from system memory at [tom-size]: [tom]) that is only accessible by the processor and only while operating in smm mode. hseg is a remap of the ab segment at feea0000 : feebffff. both of these areas, when enabled, are usable as smm ram, non-smm operations that use these address ranges are forwarded to hub interface. hseg is only enabled if lsmm = 00. 00 = tseg and hseg are both disabled 01 = tseg is disabled, hseg is conditionally enabled 10 = tseg is enabled as 512 kb and hseg is conditionally enabled 11 = tseg is enabled as 1 mb and hseg is conditionally enabled once d_lck is set, these bits becomes read only. 3:2 lower smm select ( lsmm ). this field controls the definition of the a&b segment smm space 00 = ab segment disabled 01 = ab segment enabled as general system ram 10 = ab segment enabled as smm code ram shadow. only smm code reads can access dram in the ab segment, smm data operations and all non-smm operations go to either the internal graphics device or are broadcast on hub interface. 11 = ab segment enabled as smm ram. all smm operations to the ab segment are serviced by dram, all non-smm operations go to either the internal graphics device or are broadcast on hub interface. when d_lck is set bit 3 becomes read_only, and bit 2 is writable only if bit 3 is a 1. 1 smm space locked (d_lck). when d_lck is set to 1 then d_lck, gms, usmm, and the most significant bit of lsmm become read only. d_lck can be set to 1 via a normal configuration space write but can only be cleared by a power-on reset. the combination of d_lck and lsmm provide convenience with security. the bios can use lsmm=01 to initialize smm space and then use d_lck to lock down smm space in the future so that no application software (or bios itself) can violate the integrity of smm space, even if the program has knowledge of the lsmm function. this bit also locks the drp register. 0 e_smram_err (e_smerr). this bit is set when processor accesses the defined memory ranges in extended smram (hseg or tseg) while not in smm mode. it is the softwares responsibility to clear this bit. the software must write a 1 to this bit to clear it this bit is not set for the case of an explicit write back operation.
r intel ? 82810/82810-dc100 (gmch) datasheet 47 3.4.19. miscc ? miscellaneous control register (device 0) address offset: 72C73h default value: 0000h access: read/write this register contain miscellaneous control bits for the gmch. bits[7:3] are locked (read-only) when miscc[p_clk; bit 3] = 1. 15 8 reserved 76543 10 read power throttle control write power throttle control reserved gfx local mem win size sel bit description 15:8 reserved 7:6 read power throttle control. these bits select the power throttle bandwidth limits for read operations to system memory. 00 = no limit (default) 01 = limit at 87 ? % 10 = limit at 75 % 11 = limit at 62 ? % 5:4 write power throttle control. these bits select the power throttle bandwidth limits for write operations to system memory. 00 = no limit (default) 01 = limit at 62.5% 10 = limit at 50% 11 = limit at 37.5% 3 power throttle lock (p_lck). 1 = locked. bits 7:3 of the miscc register are read-only. once this bit is set to 1, it can only be cleared to 0 by a hardware reset. 0 = not locked. 2:1 reserved. 0 graphics display cache window size select. 0 = 64 mb (default) 1 = 32 mb. see gmadr register (device 1).
intel ? 82810/82810-dc100 (gmch) r 48 datasheet 3.4.20. miscc2 ? miscellaneous control 2 register (device 0) address offset: 80h default value: 00h access: read/write this register controls miscellaneous functionality in the gmch. 73210 reserved palette load select instr. parser unit-lrvel clock enable intel reserved bit description 7:3 reserved 2 palette load select. this bit controls how the palette is loaded in the gmch. this bit must be programmed to 1 for proper operation. 1 = enable. 0 = disable. do not program to 0. 1 instruction parser unitl-level clock gating enable. this bit controls the unit-level clock gating in the instruction parser. this bit must be programmed to 1 for proper operation. 1= enable. 0 = disable. do not program to 0. 0 reserved
r intel ? 82810/82810-dc100 (gmch) datasheet 49 3.4.21. buff_scsystem memory buffer strength control register (device 0) address offset: 92C93h default value: ffffh access: read/write this register programs the system memory dram interface signal buffer strengths. the programming of these bits should be based on dram density (x8, x16, or x32), dram technology (16mb, 64mb, 128mb), rows populated, etc.. note that x4 dram are not supported,even if registered dimms are used. dimms wth ecc are also not supported and bios upon detection of ecc via spd, should report to the user that ecc dimm timings are not supported by the gmch. 15 14 13 12 11 10 9 8 scs3# buffer strength scs2# buffer strength scs1# buffer strength scs0# buffer strength smaa[7:4] buffer strength smab[7:4]# buffer strength 76543210 cke1 buffer strength cke0 buffer strength md and dqm buffer strength control buffer strength bit description 15 scs0# buffer strength. this field sets the buffer strength for system memory chip select scs0#. 0 = 3x 1 = 2x 14 scs1# buffer strength. this field sets the buffer strength for system memory chip select scs1#. 0 = 3x 1 = 2x 13 scs2# buffer strength. this field sets the buffer strength for system memory chip select scs2#. 0 = 3x 1 = 2x 12 scs3# buffer strength. this field sets the buffer strength for system memory chip select scs3#. 0 = 3x 1 = 2x 11:10 smaa[7:4] buffer strength. this field sets the buffer strength for the smaa[7:4] buffers. 00 = 4x 01 = 3x 10 = 2x 11 = 1x
intel ? 82810/82810-dc100 (gmch) r 50 datasheet bit description 9:8 smab[7:4]# buffer strength. this field sets the buffer strength for the smab[7:4]# buffers. 00 = 4x 01 = 3x 10 = 2x 11 = 1x 7:6 cke1 buffer strength. this field sets the buffer strength for the cke1 buffers. 00 = 4x 01 = 3x 10 = 2x 11 = 1x 5:4 cke0 buffer strength. this field sets the buffer strength for the cke0 buffers. 00 = 4x 01 = 3x 10 = 2x 11 = 1x 3:2 smd[63:0] and sdqm[7:0] buffer strength. this field sets the buffer strength for the smd[63:0] and sdqm[7:0] pins. 00 = 2.5x 01 = 1.5x 10 = 1x 11 = 1x 1:0 swe#, scas#, sras#, maa[11:8, 3:0], sbs[1:0] control buffer strength. this field sets the buffer strength for the swe#, scas#, sras#, maa[11:8, 3:0], sbs[1:0] pins. 00 = 4x 01 = 3x 10 = 2x 11 = 1x
r intel ? 82810/82810-dc100 (gmch) datasheet 51 3.5. graphics device registers C (device 1) table 5 shows the gmch configuration space for device #1. table 5. gmch configuration space (device 1) address offset register symbol register name default value access 00C01h vid1 vendor identification 8086h ro 02C03h did1 device identification 7121h/7123h ro 04C05h pcicmd1 pci command register 0004h r/w 06C07h pcists1 pci status register 02b0h ro, r/wc 08h rid1 revision identification 02h ro 09h pi programming interface 00h ro 0ah subc1 sub-class code 00h ro 0bh bcc1 base class code 03h ro 0ch cls cache line size register 00h ro 0dh mlt1 master latency timer 00h ro 0eh hdr1 header type 01h ro 0fh bist bist register 00h ro 10C13h gmadr graphics memory range address 00000008h r/w 14C17h mmadr memory mapped range address 00000000h r/w 18C2bh ? reserved ? ? 2c?2dh svid subsystem v endor id 0000h r/wo 2e?2fh sid subsystem id 0000h r/wo 30?33h romadr video bios rom base address 00000000h ro 34 cappoint capabilities pointer dch ro 35?3bh ? reserved ? ? 3ch intrline interrupt line register 00h r/w 3dh intrpin interrupt pin register 01h ro 3eh mingnt minimum grant register 00h ro 3fh maxlat maximum latency register 00h ro 40?dbh ? reserved ? ? dc?ddh pm_capid power management capabilities id 0001h ro de?dfh pm_cap power management capabilities 0021h ro e0?e1h pm_cs power management control 0000h r/w e2?ffh ? reserved ? ?
intel ? 82810/82810-dc100 (gmch) r 52 datasheet 3.5.1. vid ? vendor identification register (device 1) address offset: 00h - 01h default value: 8086h attribute: read only the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identify any pci device. writes to this register have no effect. bit description 15:0 vendor identification number. this is a 16-bit value assigned to intel. 3.5.2. did ? device identification register (device 1) address offset: 02h - 03h default value: 82810 = 7121h 82810-dc100 = 7123h attribute: read only this 16-bit register combined with the vendor identification register uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 device identification number. this is a 16 bit value assigned to the internal graphics device of the gmch.
r intel ? 82810/82810-dc100 (gmch) datasheet 53 3.5.3. pcicmd ? pci command register (device 1) address offset: 04h - 05h default: 0004h access: read only, read/write this 16-bit register provides basic control over the gmchs ability to respond to pci cycles. the pcicmd register in the gmch disables the gmch pci compliant master accesses to system memory. 15 10 9 8 reserved (0) fb2b (not impl) serr en (not impl) 76543210 addr/data steppin g (not impl) parity error en (not impl) vga pal sn (not impl) mem wr & inval en (not impl) special cycle en (not impl) bus master en (enabled) mem acc en i/o acc en bit descriptions 15:10 reserved . 9 fast back-to-back (fb2b) ? ro. (not implemented). hardwired to 0. 8 serr# enable (serre) ? ro. (not implemented). hardwired to 0. 7 address/data stepping ? ro. (not implemented). hardwired to 0. 6 parity error enable (perre) ? ro. (not implemented). hardwired to 0. 5 video palette snooping (vps) ? ro. this bit is hardwired to 0 to disable snooping. 4 memory write and invalidate enable (mwie) ? ro. hardwired to 0. the internal graphics device of the gmch does not support memory write and invalidate commands. 3 special cycle enable (sce) ? ro. this bit is hardwired to 0. the internal graphics device of the gmch ignores special cycles. 2 bus master enable (bme) ? ro. hardwired to 1 to enable the internal graphics device of the gmch to function as a pci compliant master. 1 memory access enable (mae) ? r/w. this bit controls the internal graphics device of the gmchs response to memory space accesses. 0 = disable (default). 1 = enable. 0 i/o access enable (ioae) ? r/w. this bit controls the internal graphics device of the gmchs response to i/o space accesses. 0 = disable (default). 1 = enable.
intel ? 82810/82810-dc100 (gmch) r 54 datasheet 3.5.4. pcists ? pci status register (device 1) address offset: 06h - 07h default value: 02b0h access: read only pcists is a 16-bit status register that reports the occurrence of a pci compliant master abort and pci compliant target abort. pcists also indicates the devsel# timing that has been set by the gmch hardware. 15 14 13 12 11 10 9 8 detected par error (hw=0) sig sys error (hw=0) recog mast abort sta (hw=0) rec target abort sta (hw=0) sig target abort sta (hw=0) devsel# timing (hw=01) data par detected (hw=0) 76543 0 fb2b (hw=1) reserved reserved cap list (hw=1) reserved bit descriptions 15 detected parity error (dpe) ? ro. since the internal graphics device of the gmch does not detect parity, this bit is always set to 0. 14 signaled system error (sse) ? ro. the internal graphics device of the gmch device never asserts serr#, therefore this bit is hardwired to 0. 13 received master abort status (rmas) ? ro. the internal graphics device of the gmch device never gets a master abort, therefore this bit is hardwired to 0. 12 received target abort status (rtas) ? ro. . the internal graphics device of the gmch device never gets a target abort, therefore this bit is hardwired to 0. 11 signaled target abort status (stas). hardwired to 0. the internal graphics device of the gmch does not use target abort semantics. 10:9 devsel# timing (devt) ? ro. this 2-bit field indicates the timing of the devsel# signal when the internal graphics device of the gmch responds as a target. hardwired to 01 to indicate that the internal graphics device of the gmch is a medium decode device. 8 data parity detected (dpd) ? r/wc. since parity error response is hardwired to disabled (and the internal graphics device of the gmch does not do any parity detection), this bit is hardwired to 0 . 7 fast back-to-back (fb2b). hardwired to 1. the internal graphics device of the gmch accepts fast back-to-back when the transactions are not to the same agent. 6:5 reserved. 4 cap list ? ro. this bit is set to 1 to indicate that the register at 34h provides an offset into the functions pci configuration space containing a pointer to the location of the first item in the list. 3:0 reserved.
r intel ? 82810/82810-dc100 (gmch) datasheet 55 3.5.5. rid ? revision identification register (device 1) address offset: 08h default value: 02h access: read only this register contains the revision number of the internal graphics device of the gmch. these bits are read only and writes to this register have no effect. bit description 7:0 revision identification number. this is an 8-bit value that indicates the revision identification number for the internal graphics device of the gmch. the four lsbs are for process differentiation and the four msbs indicate stepping. for the a-2 stepping, this value is 02h 3.5.6. pi-programming interface register (device 1) address offset: 09h default value: 00h access: read only this register contains the device programming interface information for the gmch. bit description 7:0 programming interface (pi). 00h=hardwired as a display controller. 3.5.7. subc1sub-class code register (device 1) address offset: 0ah default value: 00h access: read only size: 8 bits this register contains the sub-class code for the gmch function #1. this code is 00h indicating a vga compatible device. the register is read only. bit description 7:0 sub-class code (subc) . this is an 8-bit value that indicates the category of display controller of the gmch. the code is 00h indicating a vga compatible device.
intel ? 82810/82810-dc100 (gmch) r 56 datasheet 3.5.8. bcc1base class code register (device 1) address offset: 0bh default value: 03h access: read only size: 8 bits this register contains the base class code of the gmch function #1. this code is 03h indicating a display controller. this register is read only. bit description 7:0 base class code (basec) . this is an 8-bit value that indicates the base class code for the gmch. this code has the value 03h, indicating a display controller. 3.5.9. cls ? cache line size register (device 1) address offset: 0ch default value: 00h access: read only the internal graphics device of the gmch does not support this register as a pci slave. bit description 7:0 cache line size (cls). this field is hardwired to 0s. the internal graphics device of the gmch as a pci compliant master does not use the memory write and invalidate command and, in general, does not perform operations based on cache line size. 3.5.10. mlt ? master latency timer register (device 1) address offset: 0dh default value: 00h access: read only the internal graphics device of the gmch does not support the programmability of the master latency timer because it does not perform bursts. bit description 7:0 master latency timer count value. hardwired to 0s.
r intel ? 82810/82810-dc100 (gmch) datasheet 57 3.5.11. hdr ? header type register (device 1) address offset: 0eh default value: 00h access: read only this register contains the header type of the internal graphics device of the gmch. bit description 7:0 header type (htype). this is an 8-bit value that indicates the header type for the internal graphics device of the gmch. this code has the value 00h, indicating a basic (i.e., single function) configuration space format. 3.5.12. bist ? built in self test (bist) register (device 1) address offset: 0fh default value: 00h access: read only this register is used for control and status of built in self test (bist) for the internal graphics device of the gmch. 76 0 bist supported (hw=0) reserved bit descriptions 7 bist supported. bist is not supported. this bit is hardwired to 0. 6:0 reserved .
intel ? 82810/82810-dc100 (gmch) r 58 datasheet 3.5.13. gmadr ? graphics memory range address register (device 1) address offset: 10 - 13h default value: 00000008h access: read/write, read only this register requests allocation for the internal graphics device of the gmch local memory. the allocation is for either 32 mb or 64 mb of memory space (selected by bit 0 of the device 0 miscc register) and the base address is defined by bits [31:25,24]. 31 26 25 24 16 memory base address (addr bits [31:26]) 64 mb addr mask address mask (hw=0; 32mb addr range) 15 4 3 2 1 0 address mask (cont) (hw=0; 32mb addr range) prefetch mem en (hw=1) memory type (hw=0; 32mb addr) mem/io space (hw=0) bit descriptions 31:26 memory base address ? r/w. set by the os, these bits correspond to address signals [31:26]. 25 64m address maskro , r/w. if device 0 miscc reg bit 0 = 0 then this bit is read only with a value of 0, indicating a memory range of 64mb, if device 0 miscc reg bit 0 = 1 then this bit is r/w, indicating a memory range of 32 mb. 24:4 address mask ? ro. hardwired to 0s to indicate 32 mb address range. 3 prefetchable memory ? ro. hardwired to 1 to enable prefetching. 2:1 memory type ? ro. hardwired to 0 to indicate 32-bit address. 0 memory/io space ? ro. hardwired to 0 to indicate memory space.
r intel ? 82810/82810-dc100 (gmch) datasheet 59 3.5.14. mmadr ? memory mapped range address register (device 1) address offset: 14 - 17h default value: 00000000h access: read/write, read only this register requests allocation for the internal graphics device of the gmch registers and instruction ports. the allocation is for 512 kb and the base address is defined by bits [31:19]. 31 19 18 16 memory base address (addr bits [31:19]) address mask (hw=0; 512 kb addr range) 15 4 3 2 1 0 address mask (cont) (hw=0; 512 kb addr range) prefetch mem en (hw=0) memory type (hw=0; 32 mb addr) mem/io space (hw=0) bit descriptions 31:19 memory base address ? r/w. set by the os, these bits correspond to address signals [31:19]. 18:4 address mask ? ro. hardwired to 0s to indicate 512 kb address range. 3 prefetchable memory ? ro. hardwired to 0 to prevent prefetching. 2:1 memory type ? ro. hardwired to 0s to indicate 32-bit address. 0 memory / io space ? ro. hardwired to 0 to indicate memory space. 3.5.15. svid ? subsystem vendor identification register (device 1) address offset: 2c - 2dh default value: 0000h access: read/write once bit descriptions 15:0 subsystem vendor idr/wo. this value is used to identify the vendor of the sub system. the default value is 0000h. this field should be programmed by bios during boot-up. once written, this register becomes read only. this register can only be cleared by a reset.
intel ? 82810/82810-dc100 (gmch) r 60 datasheet 3.5.16. sid ? subsystem identification register (device 1) address offset: 2e - 2fh default value: 0000h access: read/write once bit descriptions 15:0 subsystem idr/wo. this value is used to identify a particular sub system. the default value is 0000h. this field should be programmed by bios during boot-up. once written, this register becomes read only. this register can only be cleared by a reset. 3.5.17. romadr ? video bios rom base address registers (device 1) address offset: 30 - 33h default value: 00000000h access: read only the internal graphics device of the gmch does not use a separate bios rom, therefore this is hardwired to 0s. 31 18 17 16 rom base address (addr bits [31:19]) address mask (hw=0; 256 kb addr range) 15 11 10 1 0 address mask (cont) (hw=0; 256 kb addr range) reserved (hw=0) rom bios en (hw=0) bit descriptions 31:18 rom base address ? ro. hardwired to 0s. 17:11 address mask ? ro. hardwired to 0s to indicate 256 kb address range. 10:1 reserved. hardwired to 0s. 0 rom bios enable ? ro. 0 = rom not accessible. 3.5.18. cappoint ? capabilities pointer register (device 1) address offset: 34h default value: dch access: read only bit descriptions 7:0 pointer to the atart of agp register block. since there is no agp bus on the gmch, this field is set to dch to point to the power management capabilities id register
r intel ? 82810/82810-dc100 (gmch) datasheet 61 3.5.19. intrline ? interrupt line register (device 1) address offset: 3ch default value: 00h access: read/write bit descriptions 7:0 interrupt connection. used to communicate interrupt line routing information. post software writes the routing information into this register as it initializes and configures the system. the value in this register indicates which input of the system interrupt controller that the devices interrupt pin is connected. 3.5.20. intrpin ? interrupt pin register (device 1) address offset: 3dh default value: 01h access: read only bit descriptions 7:0 interrupt pin. as a single function device, gmch specifies inta# as its interrupt pin. 01h=inta#. 3.5.21. mingnt ? minimum grant register (device 1) address offset: 3eh default value: 00h access: read only bit descriptions 7:0 minimum grant value. gmch does not burst as a pci compliant master. bits[7:0]=00h. 3.5.22. maxlat ? maximum latency register (device 1) address offset: 3fh default value: 00h access: read only bit descriptions 7:0 maximum latency value. bits[7:0]=00h. the gmch has no specific requirements for how often it needs to access the pci bus.
intel ? 82810/82810-dc100 (gmch) r 62 datasheet 3.5.23. pm_capid ? power management capabilities id register (device 1) address offset: dch - ddh default value: 0001h access: read only 15 8 7 0 next_ptr cap_id bits description 15:8 next_ptr. this contains a pointer to next item in capabilities list. this the final capability in the list and must be set to 00h. 7:0 cap_id. sig defines this id is 01h for power management. 3.5.24. pm_cap ? power management capabilities register (device 1) address offset: deh - dfh default value: 0021h access: read only 15 11 10 9 8 pme support (hw=0) d2 (hw=0) d1 (hw=0) reserved 765432 0 reserved dev specific init (hw=1) aux pwr src (hw=0) pme clock (hw=0) version (hw=001) bits description 15:11 pme support. this field indicates the power states in which the gmch may assert pme#. hardwired to 0 to indicate that the gmch does not assert the pme# signal. 10 d2. hardwired to 0 to indicate d2 power management state is not supported. 9 d1. hardwired to 0 to indicate that d1 power management state is not supported. 8:6 reserved. read as 0s. 5 device specific initialization (dsi). hardwired to 1 to indicate that special initialization of the gmch is required before generic class device driver is to use it. 4 auxiliary power source. hardwired to 0. 3 pme clock. hardwired to 0 to indicate the gmch does not support pme# generation. 2:0 version. hardwired to 001b to indicate there are 4 bytes of power management registers implemented.
r intel ? 82810/82810-dc100 (gmch) datasheet 63 3.5.25. pm_cspower management control/status register (device 1) address offset: e0h - e1h default value: 0000h access: read/write 15 14 13 12 9 8 pme sta (hw=0) data scale (reserved) data_select (reserved) pme en 7 21 0 reserved powerstate bits description 15 pme_status ? r/wc. this bit is 0 to indicate that the gmch does not support pme# generation from d3 (cold). 14:13 data scale (reserved) ? ro. the gmch does not support data register. this bit always returns 0 when read, write operations have no effect. 12:9 data_select (reserved) ? ro . the gmch does not support data register. this bit always returns 0 when read, write operations have no effect. 8 pme_en ? r/w. this bit is 0 to indicate that pme# assertion from d3 (cold) is disabled. 7:2 reserved. always returns 0 when read, write operations have no effect. 1:0 powerstate ? r/w. this field indicates the current power state of the gmch and can be used to set the gmch into a new power state. if software attempts to write an unsupported state to this field, write operation must complete normally on the bus, but the data is discarded and no state change occurs. 00 = d0 01 = reserved 10 = reserved 11 = d3
intel ? 82810/82810-dc100 (gmch) r 64 datasheet 3.6. display cache interface (82810-dc100 only) the display cache (dc) interface control registers are located in memory space. this section describes the dc interface registers. these registers are accessed using [mmadr+offset]. these registers are only memory mapped (not i/o mapped). the memory map for the 03000hC0ffffh address offset range is shown in table 6. table 6. memory map for 03000hC0ffffh address offset range address offset register symbol register name default value access 03000h drt dram row type 00h r/w 03001h dramcl dram control low 17h r/w 03002h dramch dram control high 08h r/w 03003hC03fffh ? intel reserved ? ? 04000h?06017h ? intel reserved ? ? 07000h?0ffffh ? reserved ? ? 3.6.1. drtdram row type memory offset address: 3000h default value: 00h access: read / write size: 8 bit this 8-bit register identifies whether or not the display cache is populated. memory mapped only. 7 10 reserved dram populated bit description 7:1 reserved 0 dram populated (dp). the bit in this register indicates whether or not the display cache is populated. 0 = no display cache 1 = 4mb display cache
r intel ? 82810/82810-dc100 (gmch) datasheet 65 3.6.2. dramcldram control low memory offset address: 3001h default value: 17h access: read / write size: 8 bit 7 543210 reserved paging mode control ras-to- cas override cas# latency ras# riming ras# precharge timing bit description 7:5 reserved 4 paging mode control (pmc) 0 = page open mode. in this mode the gmch memory controller tends to leave pages open. 1 = page close mode. in this mode the gmch memory controller tends to leave pages closed. 3 ras-to-cas override (rco). in units of display cache clock periods indicates the ras#-to-cas# delay (t rcd ). (i.e., row activate command to read/write command) 0 = determined by cl bit (default) 1 = 2 2 cas# latency (cl). in units of local memory clock periods. bit cl ras#-to-cas# delay (t rcd ) 0 2 2 1 3 3 (default) 1 ras# timing (rt). this bit controls ras# active to precharge, and refresh to ras# active delay (in local memory clocks). bit ras# act. to precharge (t ras ) refresh to ras# act. (t rc ) 0 5 8 1 7 10 (default) 0 ras# precharge timing (rpt). this bit controls ras# precharge (in local memory clocks). 0 = 2 1 = 3 (default)
intel ? 82810/82810-dc100 (gmch) r 66 datasheet 3.6.3. dramchdram control high memory offset address: 3002h default value: 08h access: read / write size: 8 bit 754320 reserved dram refresh rate special mode select bit description 7:5 reserved 4:3 dram refresh rate (drr). dram refresh is controlled using this field. disabling refresh results in the eventual loss of dram data, although refresh can be briefly disabled without data loss. the field must be set to normal refresh as soon as possible once dram testing is completed. 00 = refresh disabled 01 = refresh enabled (default) 10 = reserved 11 = reserved 2:0 special mode select (sms). these bits select special sdram modes used for testing and initialization. the nop command must be programmed first before any other command can be issued. 000 = normal sdram mode (normal, default). 001 = nop command enable (nce). this state forces cycles to dram to generate sdram nop commands. 010 = all banks precharge command enable (abpce). this state forces cycles to dram to generate an all banks precharge command. 011 = mode register command enable (mrce). this state forces all cycles to dram to be converted into mrs commands. the command is driven on the lma[11:0] lines. lma[2:0] correspond to the burst length, lma[3] corresponds to the wrap type, and lma[6:4] correspond to the latency mode. lma[11:7] are driven to 00000 by the gmch, the bios must select an appropriate host address for each row of memory such that the right commands are generated on the lma[6:0] lines, taking into account the mapping of host addresses to display cache addresses. 100 = cbr cycle enable (cbrce). this state forces cycles to dram to generate sdram cbr refresh cycles. 101 = reserved. 11x = reserved.
r intel ? 82810/82810-dc100 (gmch) datasheet 67 3.7. display cache detect and diagnostic registers (82810-dc100 only) the following registers are used for display cache detection and diagnostics. these registers can be accessed via either i/o space or memory space. the memory space addresses listed are offsets from the base memory address programmed into the mmadr register (device 1, pci configuration offset 14h). for each register, the memory-mapped address offset is the same address value as the i/o address. 3.7.1. grx ? grx graphics controller index register i/o (and memory offset) address: 3ceh default: 0uh (u=undefined) attributes: read/write 7430 reserved (0000) graphics controller register index bit description 7:4 reserved. read as 0s. 3:0 sequencer register index. this field selects any one of the graphics controller registers (gr[00:08) to be accessed via the data port at i/o location 3cfh.
intel ? 82810/82810-dc100 (gmch) r 68 datasheet 3.7.2. msr ? miscellaneous output i/o (and memory offset) address: 3c2h ? write; 3cch ? read default: 00h attributes: see address above 7210 reserved a0000h - bffffh acc en reserved bit descriptions 7:2 reserved 1 a0000 - bffffh access enable. vga compatibility bit enables access to the display cache at a0000h - bffffh. when disabled, accesses to system memory are blocked in this region (by not asserting devsel#). this bit does not block processor access to the video linear frame buffer at other addresses. 0 = prevent processor access to the display cache (default). 1 = allow processor access to display cache. 0 reserved
r intel ? 82810/82810-dc100 (gmch) datasheet 69 3.7.3. gr06 ? miscellaneous register i/o (and memory offset) address: 3cfh (index=06h) default: 0uh (u=undefined) attributes: read/write 743210 reserved memory map mode reserved bit description 7:4 reserved 3:2 memory map mode. these 2 bits control the mapping of the vga frame buffer into the processor address space as follows: 00 = a0000h - bffffh 01 = a0000h - affffh 10 = b0000h - b7fffh 11 = b8000h - bffffh note: this function is both in standard vga modes and in extended modes that do not provide linear frame buffer accesses. 1:0 reserved
intel ? 82810/82810-dc100 (gmch) r 70 datasheet 3.7.4. gr10 ? address mapping i/o (and memory offset) address: 3cfh (index=10h) default: 00h attributes: r/w 75 4 3210 reserved paging to display cache vga buffer /memory map packed mode enbl linear mapping page mapping bit description 7:5 reserved 4 page to display cache enable. 0 = page to vga buffer. 1 = page to display cache. 3 vga buffer/memory map select. 0 = vga buffer (default) 1 = memory map. 2 packed mode enable. 0 = disable (default) 1 = enable 1 linear mapping (pci). 0 = disable (default) 1 = enable 0 page mapping enable. this mode allows the mapping of the vga space allocated in main memory (non local video memory) mode or all of local memory space through the a0000:affff window that is a 64 kb page. 0 = disable (default) 1 = enable 3.7.5. gr11 ? page selector i/o (and memory offset) address: 3cfh (index=11h) default: 00h attributes: r/w bit description 7:0 page select. selects a 64kb window within the display cache when page mapping is enabled to the display cache.
r intel ? 82810/82810-dc100 (gmch) datasheet 71 4. functional description this chapter describes the graphics and memory controller hub (gmch) interfaces on-chip functional units. section 4.1, system address map provides a system-level address memory map and describes the memory space controls provided by the gmch. 4.1. system address map an intel celeron tm processor system based on the gmch, supports 4 gb of addressable memory space and 64 kb+3 of addressable i/o space. (the p6 bus i/o addressability is 64kb + 3). there is a programmable memory address space under the 1 mb region that can be controlled with programmable attributes of write only, or read only. attribute programming is described in the configuration register description section. this section focuses on how the memory space is partitioned and what these separate memory regions are used for. the i/o address space is discussed in section 4.1.3. the intel celeron tm processor supports addressing of memory ranges larger than 4 gb. the gmch host bridge claims any access over 4 gb by terminating the transaction (without forwarding it to the hub interface). writes are terminated by dropping the data, and for reads, the gmch returns all zeros on the host bus. in the following sections, it is assumed that all of the compatibility memory ranges reside on the hub interface. the exceptions to this rule are the vga ranges that may be mapped to the internal graphics device. note: the gmch memory map includes a number of programmable ranges, all of these ranges must be unique and non-overlapping. there are no hardware interlocks to prevent problems in the case of overlapping ranges. accesses to overlapped ranges may produce indeterminate results. 4.1.1. memory address ranges figure 4 shows a high-level representation of the system memory address map. figure 5 provides additional details on mapping specific memory regions as defined and supported by the gmch chipset. figure 4. system memory address map top of the main memor y pci memor y address ran g e 4 gb 0 independentl y pro g rammable non- overlappin g memor y windows mem_map_s.vsd local memor y ran g e memor y mapped ran g e main memor y address ran g e
intel ? 82810/82810-dc100 (gmch) r 72 datasheet figure 5. detailed memory system address map mem_map2.vsd dos area (640 kb) 000000h 0a0000h 09ffffh 0c0000h 0bffffh 0d0000h 0cffffh 0e0000h 0dffffh 0fffffh 1 mb 896 kb 832 kb 768 kb 640 kb 0 kb 0f0000h 0effffh 960 kb 0dc000h 0dbfffh 880 kb main memory 00000h a0000h 9ffffh bffffh system/application sw graphics adapter (128 kb) c0000h video bios (shadowed in memory) 100000h 0fffffh dos compatibility memory 1 mb optionally mapped to the internal gc std pci/isa video mem (smm mem) 128 kb segment c (bios shadow area, etc.) segment d (bios shadow area, etc.) optional cd hole segment e (bios shadow area, etc.) segment f (bios shadow area, etc.) 4 gb system memory space graphics (virtual) memory (32mb/64mb) size=32/64mb; miscc reg. (72h); dev 0 base=mmadr reg. (14h); dev 1 64 gb extended cpu memory space pci memory accesses to graphics (virtual) memory pci memory accesses to gc registers pci memory pci memory graphics controller (gc) (memory-mapped control/status registers) pci memory optional tseg size=0kb/512kb/1mb; smram reg. (70h); dev 0 tom (512 mb max.) pci memory optional hseg feea 0000h fee9 ffffh feec 0000h feeb ffffh base=gmadr reg. (10h); dev 1 size=512 kb C fixed optional graphics device optional isa hole 15 mb 16 mb size=0kb/512kb/1mb; smram reg. (70h); dev 0 4.1.1.1. compatibility area this area is divided into the following address regions: 0C640 kb dos area 640C768 kb video buffer area 768 kbC1 mb memory (bios area). system bios area, extended system bios area, and expansion area
r intel ? 82810/82810-dc100 (gmch) datasheet 73 table 7 lists the memory segments of interest in the compatibility area. four of the memory ranges can be enabled or disabled independently for both read and write cycles. one segment (0dc000h to 0dffffh) is conditionally mapped to the pci bus (via the hub interface). table 7. memory segments and their attributes memory segments attributes comments 000000hC09ffffh fixed - always mapped to main dram 0 to 640k - dos region 0a0000hC0bffffh mapped to pci - configurable as smm space video buffer (physical dram configurable as smm space) 0c0000hC0cffffh r/w, wo, ro, disabled bios etc shadow area 0d0000hC0dffffh r/w, wo, ro, disabled bios etc shadow area 0dc000hC0dffffh included in above or disabled bios etc shadow area, memory hole 0e0000hC0effffh r/w, wo, ro, disabled bios etc shadow area 0f0000hC0fffffh r/w, wo, ro, disabled bios etc shadow area dos area (00000h C 9ffffh). the 640 kb dos area is always mapped to the main memory controlled by the gmch. video buffer area (a0000h C bffffh). the 128 kbyte graphics adapter memory region is normally mapped to a legacy video device (e.g., vga controller) on pci via the hub interface. this area is not controlled by the attribute bits and processor -initiated cycles in this region are forwarded to hub interface or the internal graphics device for termination. this region is also the default region for smm space. accesses to this range are directed to either pci (via the hub interface) or the internal graphics device based on the configuration specified in smram[gms bits] (gmch device #0 configuration register) with additional steering information coming from the device #1 configuration registers and from some of the vga registers in the graphics device. the control is applied for accesses initiated from any of the system interfaces (i.e., host bus or hub interface). for more details, see the descriptions in the pci configuration registers specified above. smram controls how smm accesses to this space are treated. monochrome adapter (mda) range (b0000h C b7fffh). smram[gms bits] (device #0), pcicmd register bits of device #1, and bits in some of the vga registers control this functionality. ( see section 4.1.1.2). cd hole (dc000h C dffffh). gmchcfg[cdhen] (device 0) controls the routing of accesses in this region. when cdhen = 1, all accesses to the address range 000dc000hC000dffffh are forwarded on to pci, independent of the programming of the pam register. when cdhen = 0, the cd hole region is controlled by bits [3:2] of the pam register. bios etc shadow area (c0000h C fffffh). except for the cd hole area, access to this range is controlled by the bits of the pamr register bits.
intel ? 82810/82810-dc100 (gmch) r 74 datasheet 4.1.1.2. extended memory area this memory area covers the 100000h (1 mb) to ffffffffh (4 gb-1) address range and it is divided into regions as specified in the following sections. main dram address region (0010_0000h to top of main memory) the address range from 1 mb to the top of main memory is mapped to main the dram address range controlled by the gmch. all accesses to addresses within this range, except those listed below, are forwarded by the gmch to dram. optional isa memory hole (15 mb C 16 mb). a 1 mb isa memory hole in the main dram range can be enabled via the fdhc register (device 0). note that this memory is not re-mapped. accesses to this range are forwarded to pci (via the hub interface) tseg. this extended smram address range, if enabled, occupies the 512 kb or 1 mb range below the top of main memory. the size of tseg is determined by smram[usmm] (device 0). when the extended smram space is enabled, non-smm processor accesses and all other accesses in this range are forwarded to pci (via the hub interface). when smm is enabled, the amount of memory available to the system is reduced by the tseg range. optional graphics device memory. this address range provides either 512kb or 1mb of vga buffer memory for the internal graphics device . if tseg is enabled, this address range is just below tseg. if tseg is not enabled, the optional graphics device vga buffer range is just below tom. the graphics device buffer memory range is enabled and the size selected via smram[gms]. pci memory address region (top of main memory to 4 gb) the address range from the top of main dram to 4 gb (top of physical memory space supported by the gmch) is normally mapped to pci (via the hub interface), except for the address ranges listed below. there are two sub-ranges within the pci memory address range defined as apic configuration space and high bios address range. the local memory range and the memory mapped range of the internal graphics device must not overlap with these two ranges. gmchs graphics controller status/control register range. a 512 kb space ( error! reference source not found. ) for the graphics controller devices memory-mapped status/control registers is requested during plug and play. the base address is programmed in the mmadr pci configuration register for device 1. note that, for legacy support, the vga registers in the gmchs graphics controller are also mapped to the normal i/o locations.
r intel ? 82810/82810-dc100 (gmch) datasheet 75 figure 6. gmch graphics register memory address space reginstm.vsd intel reserved display cache interface control registers 00000h 00fffh 01000h vga and ext. vga registers vga and ext. vga registers i/o space map (standard graphics locations) memory space map (512 kb allocation) offset from base_reg intel reserved 06fffh 07000h 02fffh 03000h 03fffh 04000h 0ffffh 10000h 1ffffh 20000h 2ffffh 30000h intel reserved 7ffffh intel reserved mmadr register (base address) 19 31 graphics controller graphics memory range. the gmchs graphics controller device uses a logical memory concept to access graphics memory. the logical graphics memory size is programmable as either 32 mb or 64 mb and is allocated by bios during plug and play. this address range is programmed in the gmadr register (device 1) and the miscc register (device 0). the graphics controller engines can access this address space (the lower 32 mb or all 64 mb correspond to graphics memory that is accessable by the processor). apic configuration space (fec0_0000h C fecf_ffffh, fee0_0000h C feef_ffffh). this range is reserved for apic configuration space that includes the default i/o apic configuration space. the default local apic configuration space is fee0_0000h to feef_0fffh. processor accesses to the local apic configuration space do not result in external bus activity since the local apic configuration space is internal to the processor. however, a mtrr must be programmed to make the local apic range uncacheable (uc). the local apic base address in each processor should be relocated to the fec0_0000h (4gbC20mb) to fecf_ffffh range so that one mtrr can be programmed to 64 kb for the local and i/o apics. the i/o apic(s) usually reside in the i/o bridge portion of the chipset or as a stand-alone component(s). i/o apic units are located beginning at the default address fec0_0000h. the first i/o apic is located at fec0_0000h. each i/o apic unit is located at fec0_x000h where x is i/o apic unit number 0 through f(hex). this address range is normally mapped via hub interface to pci. the address range between the apic configuration space and the high bios (fed0_0000h to fedf_ffffh) is always mapped to pci (via the hub interface).
intel ? 82810/82810-dc100 (gmch) r 76 datasheet high bios area (ffe0_0000h C ffff_ffffh). the top 2 mb of the extended memory region is reserved for system bios (high bios), extended bios for pci devices, and the a20 alias of the system bios. processor begins execution from the high bios after reset. this region is mapped to pci (via the hub interface) so that the upper subset of this region aliases to 16 mbC256 kb range . the actual address space required for the bios is less than 2 mb but the minimum processor mtrr range for this region is 2 mb so that full 2 mb must be considered. the ich supports a maximum of 1 mb in the high bios range. optional hseg. this extended smram address range, if enabled via the smram register, occupies the range from feea_0000h to feeb_ffffh. maps to a0000hCbffffh when enabled. 4.1.1.3. system management mode (smm) memory range the gmch supports the use of main memory as system management ram (smram), enabling the use of system management mode. the gmch supports two smram options: compatible smram (c_smram) and extended smram (e_smram). system management ram (smram) space provides a memory area that is available for the smi handler's and code and data storage. this memory resource is normally hidden from the system os so that the processor has immediate access to this memory space upon entry to smm. the gmch provides three smram options: below 1 mb option that supports compatible smi handlers. above 1 mb option that allows new smi handlers to execute with write-back cacheable smram. optional larger write-back cacheable t_seg area of either 512 kb or 1mb in size above 1 mb that is reserved from the highest area in system dram memory. the above 1 mb solutions require changes to compatible smram handlers code to properly execute above 1 mb. refer to the power management section for more details on smram support. 4.1.2. memory shadowing any block of memory that can be designated as read-only or write-only can be shadowed into the gmch dram memory. typically, this is done to allow rom code to execute more rapidly out of main dram. rom is used as a read-only during the copy process while dram at the same time is designated write-only. after copying, the dram is designated read-only so that rom is shadowed. processor bus transactions are routed accordingly.
r intel ? 82810/82810-dc100 (gmch) datasheet 77 4.1.3. i/o address space the gmch does not support the existence of any other i/o devices besides itself on the processor bus. the gmch generates hub interface bus cycles for all processor i/o accesses that do not target the legacy i/o registers supported by the internal graphics device. the gmch contains two internal registers in the processor i/o space, configuration address register (config_address) and the configuration data register (config_data). these locations are used to implement pci configuration space access mechanism as described in the registers section of this document. the processor allows 64k+3 bytes to be addressed within the i/o space. the gmch propagates the processor i/o address without any translation to the destination bus and therefore provides addressability for 64k+3 byte locations. note that the upper 3 locations can be accessed only during i/o address wrap- around when processor bus a16# address signal is asserted. a16# is asserted on the processor bus whenever an i/o access is made to 4 bytes from address 0fffdh, 0fffeh, or 0ffffh. a16# is also asserted when an i/o access is made to 2 bytes from address 0ffffh. the i/o accesses, other than ones used for pci configuration space access or ones that target the internal graphics device are forwarded to hub interface. the gmch does not post i/o write cycles to ide. the gmch does not respond to i/o cycles initiated on hub interface. 4.1.4. gmch decode rules and cross-bridge address mapping the gmchs address map applies globally to accesses arriving on any of the three interfaces (i.e., host bus, hub interface or from the internal graphics device). hub interface decode rules the gmch accepts all memory read and write accesses from hub interface to both system memory and graphics memory. hub interface accesses that fall elsewhere within the pci memory range are not accepted. the gmch does not respond to hub interface-initiated i/o read or write cycles. legacy vga ranges the legacy vga memory range a0000hCbffffh is mapped either to the internal graphics device or to hub interface depending on the programming of the gms bits in the smram configuration register in gmch device #0, and some of the bits in the vga registers of the internal graphics device. these same bits control mapping of vga i/o address ranges. vga i/o range is defined as addresses where a[9:0] are in the ranges 3b0h to 3bbh and 3c0h to 3dfh (inclusive of isa address aliases - a[15:10] are not decoded). these bits control all accesses to the vga ranges, including support for mda functionality. i/o accesses to location 3bfh are always forwarded on to hub interface.
intel ? 82810/82810-dc100 (gmch) r 78 datasheet 4.2. host interface the host interface of the gmch is optimized to support the intel celeron tm processor. the gmch implements the host address, control, and data bus interfaces within a single device. the gmch supports a 4-deep in-order queue (i.e., supports pipelining of up to 4 outstanding transaction requests on the host bus) . host bus addresses are decoded by the gmch for accesses to system memory, pci memory & pci i/o (via hub interface), pci configuration space and graphics memory. the gmch takes advantage of the pipelined addressing capability of the processor to improve the overall system performance. the gmch supports the 370-pin socket connector. 4.2.1. host bus device support the gmch recognizes and supports a large subset of the transaction types that are defined for the intel celeron tm processor bus interface. however, each of these transaction types have a multitude of response types, some of which are not supported by this controller. all transactions are processed in the order that they are received on the processor bus.
r intel ? 82810/82810-dc100 (gmch) datasheet 79 table 8. summay of transactions supported by gmch transaction reqa[4:0]# reqb[4:0]# gmch support deferred reply 0 0 0 0 0 x x x x x the gmch initiates a deferred reply for a previously deferred transaction. reserved 0 0 0 0 1 x x x x x reserved interrupt acknowledge 0 1 0 0 0 0 0 0 0 0 interrupt acknowledge cycles are forwar ded to the hub interface. special transactions 0 1 0 0 0 0 0 0 0 1 see separate table in special cycles section. reserved 0 1 0 0 0 0 0 0 1 x reserved reserved 0 1 0 0 0 0 0 1 x x reserved branch trace message 0 1 0 0 1 0 0 0 0 0 the gmch terminates a branch trace message without latching data. reserved 0 1 0 0 1 0 0 0 0 1 reserved reserved 0 1 0 0 1 0 0 0 1 x reserved reserved 0 1 0 0 1 0 0 1 x x reserved i/o read 1 0 0 0 0 0 0 x len# i/o read cycles are forwar ded to hub interface. i/o cycles that are in the gmch configuration space are not forwarded to the hub interface. i/o write 1 0 0 0 1 0 0 x len# i/o write cycles are forwar ded to hub interface. i/o cycles that are in the gmch configuration space are not forwarded to hub interface. reserved 1 1 0 0 x 0 0 x x x reserved memory read & invalidate 0 0 0 1 0 0 0 x len# host initiated memory read cycles are forwar ded to dram or the hub interface. reserved 0 0 0 1 1 0 0 x len# reserved memory code read 0 0 1 0 0 0 0 x len# memory code read cycles are forwar ded to dram or hub interface. memory data read 0 0 1 1 0 0 0 x len# host initiated memory read cycles are forwar ded to dram or the hub interface. memory write (no retry) 0 0 1 0 1 0 0 x len# this memory write is a writeback cycle and cannot be retried. the gmch forwards the write to dram. memory write (can be retried) 0 0 1 1 1 0 0 x len# the standard memory write cycle is forwar ded to dram or hub interface. notes: 1. for memory cycles, reqa[4:3]# = asz#. gmch only s upports asz# = 00 (32 bit address). 2. reqb[4:3]# = dsz#. dsz# = 00 (64 bit data bus size). 3. len# = data transfer length as follows: len# data length 00 <= 8 bytes (be[7:0]# specify granularity) 01 length = 16 bytes be[7:0]# all active 10 length = 32 bytes be[7:0]# all active 11 reserved
intel ? 82810/82810-dc100 (gmch) r 80 datasheet table 9. host responses supported by the gmch rs2# rs1# rs0# description gmch support 000idle 0 0 1 retry response this response is generated if an access is to a resource that cannot be accessed by the processor at this time and the logic must avoid deadlock . hub interface directed reads, writes, and dram locked reads can be retried. 0 1 0 deferred response this response can be returned for all transactions that can be executed out of order. hub interface directed reads (memory, i/o and interrupt acknowledge) and writes (i/o only), and internal graphics device directed reads (memory and i/o) and writes (i/o only) can be deferred. 0 1 1 reserved reserved 1 0 0 hard failure not supported. 101no data response this is for transactions where the data has already been transferred or for transactions where no data is transferred. writes and zero length reads receive this response. 1 1 0 implicit writeback this response is given for those transactions where the initial transactions snoop hits on a modified cache line. 111normal data response this response is for transactions where data accompanies the response phase. reads receive this response.
r intel ? 82810/82810-dc100 (gmch) datasheet 81 4.2.2. special cycles a special cycle is defined when reqa[4:0] = 01000 and reqb[4:0]= xx001. the first address phase aa[35:3]# is undefined and can be driven to any value. the second address phase, ab[15:8]# defines the type of special cycle issued by the processor. table 10 specifies the cycle type and definition as well as the action taken by the gmch when the corresponding cycles are identified. table 10. special cycles be[7:0}# special cycle type action taken 0000 0000 nop this transaction has no side-effects. 0000 0001 shutdown this transaction is issued when an agent detects a severe software error that prevents further processing. this cycle is claimed by the gmch. the gmch issues a shutdown special cycle on the hub interface. this cycle is retired on the processor bus after it is terminated on the hub interface via a master abort mechanism. 0000 0010 flush this transaction is issued when an agent has invalidated its internal caches without writing back any modified lines. the gmch claims this cycle and retires it. 0000 0011 halt this transaction is issued when an agent executes a hlt instruction and stops program execution. this cycle is claimed by the gmch and propagated to the hub interface as a special halt cycle. this cycle is retired on the processor bus after it is terminated on the hub interface via a master abort mechanism. 0000 0100 sync this transaction is issued when an agent has written back all modified lines and has invalidated its internal caches. the gmch claims this cycle and retires it. 0000 0101 flush acknowledge this transaction is issued when an agent has completed a cache sync and flush operation in response to an earlier flush# signal assertion. the gmch claims this cycle and retires it. 0000 0110 stop clock acknowledge this transaction is issued when an agent enters stop clock mode. this cycle is claimed by the gmch and propagated to the hub interface as a special stop grant cycle. this cycle is completed on the processor bus after it is terminated on the hub interface via a master abort mechanism. 0000 0111 smi acknowledge this transaction is first issued when an agent enters the system management mode (smm). ab[7]# is also set at this entry point. all subsequent transactions from the processor with ab[7]# set are treated by the gmch as accesses to the smm space. no corresponding cycle is pr opagated to the hub interface. to exit the system management mode the processor issues another one of these cycles with the ab[7]# bit deasserted. the smm space access is closed by the gmch at this point. all others reserved
intel ? 82810/82810-dc100 (gmch) r 82 datasheet 4.3. system memory dram interface the gmch integrates a system dram controller that supports a 64-bit dram array. the dram type supported is synchronous (sdram). the gmch generates the scs#, sdqm, scas#, sras#, swe# and multiplexed addresses, sma for the dram array. the gmchs dram interface operates at a clock frequency of 100 mhz, independent of the system bus interface clock frequency. the dram controller interface is fully configurable through a set of control registers. complete descriptions of these registers are given in the register description section of this document. the gmch supports industry standard 64-bit wide dimm modules with sdram devices. the 2 bank select lines sbs[1:0], the 12 address lines smaa[11:0], and second copies of 4 address lines smab[7:4]# allow the gmch to support 64 bit wide dimms using 16mb, 64mb, or 128mb technology sdrams. the gmch has four scs# lines, enabling the support of up to four 64-bit rows of dram. for write operations of less than a qword in size, the gmch performs a byte-wise write. the gmch targets sdram with cl2 and cl3 and supports both single and double-sided dimms. the gmch provides refresh functionality with programmable rate (normal dram rate is 1 refresh/15.6 m s). the gmch can be configured via the page closing policy bit in the gmch configuration register to keep multiple pages open within the memory array. pages can be kept open in any one row of memory. up to 4 pages can be kept open within that row (the gmch supports 4 bank sdrams on system dram interface). 4.3.1. dram organization and configuration the gmch supports 64-bit dram configurations. in the following discussion the term row refers to a set of memory devices that are simultaneously selected by a scs# signal. the gmch supports a maximum of 4 rows of memory. both single-sided and double-sided dimms are supported. the interface consists of the following pins: multiple copies: smaa[7:4], smab[7:4]# single copies: smd[63:0] sdqm[7:0] smaa[11:8,3:0] sbs[1:0] scs[3:0]# scas# sras# swe# scke[1:0] the gmch supports dimms populated with 8, 16, and 32 bit wide sdram devices. registered dimms or dimms populated with 4-bit wide sdram devices are not supported. the gmch supports 3.3v standard sdrams.
r intel ? 82810/82810-dc100 (gmch) datasheet 83 table 11 illustrates a sample of the possible dimm socket configurations along with corresponding drp programming. see the register section of this document for a complete drp programming table. table 11. sample of possible mix and match options for 4 row/2 dimm configurations dimm0 dimm1 drp total memory 0 4x(4m x 16 ) s 70 32 mb 4x (4m x16 ) s 0 07 32 mb 4x(4mx16) + 2x(2mx32) d 0 08 48 mb 4x(4mx16) s 4x(4mx16) s 77 64 mb 8x(8mx8) + 4x(4mx16) d 0 0b 96 mb 8x(8mx8) d 0 0c 128 mb 8x(8mx8) d 8x(8mx8) d cc 256 mb notes: 1. "s" denotes single-sided dimm's, "d" denotes double-sided dimm's. 4.3.1.1. configuration mechanism for dimms detection of the type of dram installed on the dimm is supported via serial presence detect mechanism as defined in the jedec 168-pin dimm standard. this standard uses the scl, sda and sa[2:0] pins on the dimms to detect the type and size of the installed dimms. no special programmable modes are provided on the gmch for detecting the size and type of memory installed. type and size detection must be done via the serial presence detection pins. use of serial presence detection is required. memory detection and initialization before any cycles to the memory interface can be supported, the gmch dram registers must be initialized. the gmch must be configured for operation with the installed memory types. detection of memory type and size is done via the system management bus (smbus) interface on the ich. this two-wire bus is used to extract the dram type and size information from the serial presence detect port on the dram dimm modules. dram dimm modules contain a 5 pin serial presence detect interface, including scl (serial clock), sda (serial data) and sa[2:0]. devices on the smbus bus have a seven bit address. for the dram dimm modules, the upper four bits are fixed at 1010. the lower three bits are strapped on the sa[2:0] pins. scl and sda are connected directly to the system management bus on the ich. thus, data is read from the serial presence detect port on the dram dimm modules via a series of i/o cycles to the ich. bios essentially needs to determine the size and type of memory used for each of the four rows of memory to properly configure the gmch system memory interface. smbus configuration and access of the serial presence detect ports for details on smbus and serial presence detect, see the intel ? 82801aa (ich) and intel ? 82801ab (ich0) i/o controller hub datasheet .
intel ? 82810/82810-dc100 (gmch) r 84 datasheet 4.3.1.2. dram register programming this section provides an overview of how the required information for programming the dram registers is obtained from the serial presence detect ports on the dimms. the serial presence detect ports are used to determine refresh rate, ma and md buffer strength, row type (on a row by row basis), sdram timings, row sizes, and row page sizes. table 12 lists a subset of the data available through the on-board serial presence detect rom on each dimm module. table 12. data bytes on dimm used for programming dram registers byte function 2 memory type (edo, sdram) the gmch only supports sdram. 3 # of row addresses, not counting bank addresses 4 # of column addresses 5 # of banks of dram (single or double sided) dimm 12 refresh rate 17 # banks on each sdram device 36-41 access time from clock for cas# latency 1 through 7 42 data width of sdram components table 12 is only a subset of the defined spd bytes on the dimm module. these bytes collectively provide enough data for bios to program the gmch dram registers. 4.3.2. dram address translation and decoding the gmch contains address decoders that translate the address received on the host bus, hub interface, or from the internal graphics device to an effective memory address. the gmch supports 16 and 64 mbit sdram devices. the gmch supports a 2 kb page sizes only. the multiplexed row / column address to the dram memory array is provided by the sbs[1:0] and smaa[11:0] signals and copies. these addresses are derived from the host address bus as defined by by the following table for sdram devices. row size is internally computed using the values programmed in the drp register. up to 4 pages can be open at any time within any row (only 2 active pages are supported in rows populated with either 8 mbs or 16 mbs ).
r intel ? 82810/82810-dc100 (gmch) datasheet 85 table 13. gmch dram address mux function address usage mem bs smaa techdepthwidrowcolbksize 1 011109876543210 16mb 1mb 16 11 8 1 8mb x 11 x [a] 22 21 20 19 18 17 16 15 14 13 x11xpaxx109876543 16mb 2mb 8 11 9 1 16mb x 11 x [a] 22 21 20 19 18 17 16 15 14 13 x11xpax23109876543 64mb 2mb 32 11 8 2 16mb 12 11 x [a]22212019181716151413 1211xpaxx109876543 64mb 4mb 16 12 8 2 32mb 12 11 24 [a] 22 21 20 19 18 17 16 15 14 13 1211xpaxx109876543 64mb 8mb 8 12 9 2 64mb 12 11 24 [a] 22 21 20 19 18 17 16 15 14 13 12 11 x pa x 25 10 9 8 7 6 5 4 3 128mb 4mb 32 12 8 2 32mb 12 11 24 [a] 22 21 20 19 18 17 16 15 14 13 1211xpaxx109876543 128mb 8mb 16 12 9 2 64mb 12 11 24 [a] 22 21 20 19 18 17 16 15 14 13 12 11 x pa x 25 10 9 8 7 6 5 4 3 128mb 16mb 8 12 10 2 128mb 12 11 24 [a] 22 21 20 19 18 17 16 15 14 13 1211xpa2625109876543 notes: 1. [a]; ma bit 10 at ras time uses the xor of address bit 12 and address bit 23
intel ? 82810/82810-dc100 (gmch) r 86 datasheet 4.3.3. dram array connectivity figure 7. dram array sockets (2 dimm sockets) scs [ 3:2 ] # scs [ 1:0 ] # scke0 scke1 sras# scas# swe# sbs [ 1:0 ] smaa [ 11:8,3:0 ] smaa [ 7:4 ] smab [ 7:4 ] # sdqm [ 7:0 ] smd [ 63:0 ] dimm_clk [ 3:0 ] dimm_clk [ 7:4 ] smb_clk smb_data note: min ( 16mbit ) 8mb; max ( 64mbit ) 256mb; max ( 128mbit ) 512mb mem_dimm.vsd 4.3.4. sdramt register programming several dram timing parameters are programmable in the gmch configuration registers. table 14 summarizes the programmable parameters. table 14. programmable sdram timing parameters parameter dramt bit values (sclks) ras# precharge (srp) 0 2,3 ras# to cas# delay (srcd) 1 2,3 cas# latency (cl) 2 2,3 dram cycle time (dct) 4 tras = 5,6 trc = 7,8 the parameters in table 14 are controlled via the dramt register. to support different device speed grades cas# latency, ras# to cas# delay, and ras# precharge are all programmable as either two or three sclks. to provide flexibility, these parameters are each controlled by separate register bits (i.e., the gmch supports any combination of cas# latency, ras# to cas# delay and ras# precharge).
r intel ? 82810/82810-dc100 (gmch) datasheet 87 4.3.5. sdram paging policy the gmch can maintain up to 4 active pages in any one row; however, the gmch does not support active pages in more than 1 row at a time. the dram page closing policy (dpcp) in the gmch configuration register (gmchcfg) controls the page closing policy of the gmch. this bit controls whether the gmch precharges bank or precharges all during the service of a page miss. when this bit is set to 0, the gmch prechanges bank during the service of a page miss. when this bit is set to 1, the gmch prechanges all during the service of a page miss. 4.4. intel a dynamic video memory technology (d.v.m.t.) the internal graphics device on both the 82810 and 82810-dc100 support intel a dynamic video memory technology (d.v.m.t.). d.v.m.t. dynamically responds to application requirements by allocating the proper amount of display and texturing memory. for more details, refer to the document entitled intel ? 810 chipset: great performance for value pcs. this document is available at: http://developer.intel.com/design/chipsets/810/810white.htm in addition to d.v.m.t., the 82810-dc100 supports display cache (dc). the graphics engine of the 82810-dc100 uses dc for implementing rendering buffers (e.g., z-buffers). this rendering model requires 4 mb of display cache and allows graphics rendering (performed across the graphics display cache bus) and texture mip map access (performed across the system memory bus) simultaneously. using d.v.m.t., all graphics rendering is implemented in system memory. the system memory bus is arbitrated between texture mip-map accesses and rendering functions. 4.5. display cache interface (82810-dc100 only) the gmch display cache (dc) is a single channel 32 bit wide sdram interface. the dc handles the control and timing for the display cache. the display cache interface of the gmch generates the lcs#, ldqm[7:0], lscas#, lsras#, lwe#, lmd[31:0] and multiplexed addresses, lma[11:0] for the display cache dram array. the gmch also generates the clock ltclk for write cycles as well as loclk for read cycle timings. the display cache interface of the gmch supports single data rate synchronous dynamic random access memory (sdram). it supports a single 32-bit wide memory channel. the interface handles the operation of d.v.m.t. with dc at 100 mhz. the dram controller interface is fully configurable thro ugh a set of control registers. internal buffering (fifos) of the data to and from the display cache ensures the synchronization of the data to the internal pipelines. the d.v.m.t. with dc interface clocking is divided synchronous with respect to the core and system bus.
intel ? 82810/82810-dc100 (gmch) r 88 datasheet 4.5.1. supported dram types only 1mx16 sdrams are supported by the gmch. 4.5.2. memory configurations table 15 gives a summary of the characteristics of memory configurations supported. the gmch supports a 32-bit wide channel populated with a single row of 1mx16 sdrams. table 15. memory size for each configuration sdram address size tech. density width # of banks bank row column dram addressing dram size 16 mbit 1m 16 2 1 11 8 asymmetric 4mb figure 8 shows the gmch lmi connected to 4 mb of memory in a 32-bit sdram channel configuration. figure 8. gmch display cache interface to 4mb gmch (2) 1m x 16 sdram loclk lrclk ltclk ldqm[3:0] lmd[31:0] lma[11:0] lwe# lscas lsras lcs#
r intel ? 82810/82810-dc100 (gmch) datasheet 89 4.5.3. address translation the gmch contains address decoders that translate the address received by the display cache into an effective display cache address. the lma[11:0] bits are as defined below. entries in the table (e.g., a21(x)) imply that the gmch puts out a21 on that ma line but it is not used by the sdram. table 16. gmch local memory address mapping 1mx16 ma row column 11(ba) a10 a10 10 a11 x 9a21x 8a20x 7a19a9 6a18a8 5a17a7 4a16a6 3a15a5 2a14a4 1a13a3 0a12a2 ba = bank address 4.5.4. display cache interface timing the gmch provides a variety of programmable wait states for dram read and write cycles. these options are programmed in the display cache i/o addresses of the gmch configuration space. the wrap type and the burst length is implied since they are not programmable and fixed. only sequential wrap is allowed. burst length is fixed at two.
intel ? 82810/82810-dc100 (gmch) r 90 datasheet 4.6. internal graphics device 4.6.1. 3d/2d instruction processing the gmch contains an extensive set of instructions that control various functions including 3d rendering, blt and strblt operations, display, motion compensation, and overlay. the 3d instructions set 3d pipeline states and control the processing functions. the 2d instructions provide an efficient method for invoking blt and strblt operations. the graphics controller executes instructions from one of two instruction buffers located in either system memory or the display cache (82810-dc100 only): interrupt ring or low priority ring. instead of writing instructions directly to the gmchs graphics controller, software sets up instruction packets in these memory buffers and then instructs the gmch to process the buffers. the gmch uses dmas to put the instructions into its fifo and executes them. instruction flow in the ring buffer instruction stream can make calls to other buffers, much like a software program makes subroutine calls. flexibility has been built into the ring operation permitting software to efficiently maintain a steady flow of instructions. batching instructions in memory ahead of time and then instructing the graphics controller to process the instructions provides significant performance advantages over writing directly to fifos including: 1) reduced software overhead, 2) efficient dma instruction fetches from graphics memory, and 3) software can more efficiently set up instruction packets in buffers in graphics memory (faster than writing to fifos). figure 9. 3d/2d pipeline preprocessor dma fifo instr parser 3d instructions (3d state, 3d primitives, strblt, motion compensation) 2d instructions cmd_str.vsd 3d engine blt engine instruction access and decoding low priority ring (graphics memory) instruction batch buff instr batch buffers instruction display engine overlay engine interrupt ring (graphics memory) instruction batch buff instr instruction batch buffers dma dma
r intel ? 82810/82810-dc100 (gmch) datasheet 91 4.6.2. 3d engine the 3d engine of the gmch has been architected as a deep pipeline, where performance is maximized by allowing each stage of the pipeline to simultaneously operate on different primitives or portions of the same primitive. the internal graphics device of the gmch supports perspective-correct texture mapping, bilinear and anisotropic mip mapping, gouraud shading, alpha-blending, fogging and z-buffering. these features can be independently enabled or disabled via set of 3d instructions. this frees up the display cache for other uses (e.g., back and depth buffers, bitmaps, etc.). in addition, the gmch supports a dynamic video memory (d.v.m.) that allows the entire 3d rendering process to take place in system memory; thus, alleviating the need for the display cache. the main blocks of the pipeline are the setup engine, scan converter, texture pipeline, and color calculator block. a typical programming sequence would be to send instructions to set the state of the pipeline followed by rendering instructions containing 3d primitive vertex data. 4.6.3. buffers the 2d, 3d and video capabilities of the internal graphics device of the gmch provide control over a variety of graphics buffers that can be implemented either in display cache or system memory. to aid the rendering process, the display cache of the gmch contains two hardware buffersthe front buffer (display buffer) and the back buffer (rendering buffer). the image being drawn is not visible until the scene is complete and the back buffer made visible (via an instruction) or copied to the front buffer (via a 2d blt operation). by rendering to one and displaying from the other, the possibility of image tearing is removed. this also speeds up the display process over a single buffer. the 3d pipeline of the gmch operates on the back buffer and the z-buffer. the pixels 16-bit (or 15-bit) rgb colors are stored in the back buffer. the z-buffer can be used to store 16-bit depth values or 5-bit destination alpha values. the instruction set of the gmch provides a variety of controls for the buffers (e.g., initializing, flip, clear, etc.).
intel ? 82810/82810-dc100 (gmch) r 92 datasheet figure 10. data flow for the 3d pipeline depth buffer (z-buffer) system memory textures instructions and data primitives pixels mapping engine color calculator rasterize setup discard (back face culling) frame buffer gmch graphics pipeline (conceptual representation) notes: 1. frame buffer = front and back buffers 3d_pipe2.vsd a) intel ? 82810 gmch b) intel ? 82810-dc100 gmch depth buffer (z-buffer) display cache system memory textures instructions and data gmch interface primitives pixels mapping engine color calculator rasterize setup discard (back face culling) frame buffer gmch graphics pipeline (conceptual representation) gmch interface
r intel ? 82810/82810-dc100 (gmch) datasheet 93 4.6.4. setup the setup stage of the pipeline takes the input data associated with each vertex of the line or triangle primitive and computes the various parameters required for scan conversion. in formatting this data, the gmch maintains sub-pixel accuracy. data is dynamically formatted for each rendered polygon and output to the proper processing unit. as part of the setup, the gmch removes polygons from further processing, if they are not facing the users viewpoint (referred to as back face culling). 4.6.5. texturing the internal graphics device of the gmch allows an image, pattern, or video to be placed on the surface of a 3d polygon. textures must be located in system memory. being able to use textures directly from system memory means that large complex textures can easily be handled without the limitations imposed by the traditional approach of only using the display cache. the texture processor receives the texture coordinate information from the setup engine and the texture blend information from the scan converter. the texture processor performs texture color or chroma-key matching, texture filtering (anisotropic and bilinear interpolation), and yuv to rgb conversions. the gmch supports up to 11 levels-of-detail (lods) ranging in size from 1024x1024 to 1x1 texels. (a texel is defined as a texture map pixel). textures need not be square. included in the texture processor is a small cache that provides efficient mip-mapping. nearest. texel with coordinates nearest to the desired pixel is used. (this is used if only one lod is present). linear. a weighted average of a 2x2 area of texels surrounding the desired pixel are used. (this is used if only one lod is present). mip nearest. this is used if many lods are present. the appropriate lod is chosen and the texel with coordinates nearest to the desired pixel are used. mip linear. this is used if many lods are present. the appropriate lod is chosen and a weighted average of a 2x2 area of texels surrounding the desired pixel are used. this is also referred to as bi-linear mip-mapping. anisotropic. this can be used if multiple lods are present. this filtering method improves the visual quality of texture-mapped objects when viewed at oblique angles (i.e., with a high degree of perspective foreshortening). the improvement comes from a more accurate (anisotropic) mapping of screen pixels onto texels; where using bilinear or trilinear filtering can yield overly- blurred results. situations where anisotropic filtering demonstrates superior quality include text viewed at an angle, lines on roadways, etc.
intel ? 82810/82810-dc100 (gmch) r 94 datasheet the gmch can store each of the above mip-maps in any of the following formats: 8bpt surface format 16bpt surface format ? rgb 565 ? argb 1555 ? argb 4444 ? ay 88 8bpt (indexed) surface format ? rgb 565 ? argb 1555 ? argb 4444 ? ay 88 ? 4:2:2 ? ycrcb, swap y format ? ycrcb, normal ? ycrcb, uv swap ? ycrcb, uv/y swap many texture mapping modes are supported. perspective correct mapping is always performed. as the map is fitted across the polygon, the map can be tiled, mirrored in either the u or v directions, or mapped up to the end of the texture and no longer placed on the object (this is known as clamp mode). the way a texture is combined with other object attributes is also definable. texture colorkey and chromakey colorkey and chromakey describe two methods of removing a specific color or range of colors from a texture map before it is applied to an object. for nearest texture filter modes, removing a color simply makes those portions of the object transparent (the previous contents of the back buffer show through). for linear texture filtering modes, the texture filter is modified if only the non-nearest neighbor texels match the key (range). colorkeying occurs with paletted textures, and removes colors according to an index (before the palette is accessed). when a color palette is used with indices to indicate a color in the palette, the indices can be compared against a state variable colorkey index value and if a match occurs and colorkey is enabled, then this values contribution is removed from the resulting pixel color. the gmch defines index matching as colorkey. chromakeying can be performed for both paletted and non-paletted textures, and removes texels that fall within a specified color range. the chromakey mode refers to testing the rgb or yuv components to see if they fall between high and low state variable values. if the color of a texel contribution is in this range and chromakey is enabled, then this contribution is removed from the resulting pixel color. multiple texture composition the gmch includes support for two simultaneous texture maps. this support greatly reduces the need for multipass compositing techniques for effects such as diffuse light maps, specular reflection maps, bump mapping, detail textures, gloss maps, shadows, and composited effects like dirt or tire marks. supporting these techniques in hardware greatly increases compositing performance by reducing the need to read and write the frame buffer multiple times.
r intel ? 82810/82810-dc100 (gmch) datasheet 95 this multitexture support provides a superset of the legacy one-texture (pre-directx 6) texture blend modes and a large subset of the operations defined in directx 6 and the opengl arb multitexture extensions. the multitexture compositing unit is capable of combining the interpolated vertex diffuse color, a constant color value, and up to two texels per pixel in a fully-programmable fashion. up to three operations (combinations) can be performed in a pipelined organization, with intermediate storage to support complex equations, e.g., of the form a*b + c*d required for light maps and specular gloss maps. separate operations can be performed on color (rgb) and alpha components. 4.6.6. 2d operation the gmch contains blt and strblt functionality, a hardware cursor, and an extensive set of 2d registers and instructions. gmch vga registers and enhancements the 2d registers are a combination of registers defined by ibm* when the video graphics array (vga) was first introduced, and others that intel has added to support graphics modes that have color depths, resolutions, and hardware acceleration features that go beyond the original vga standard. the internal graphics device of the gmch improves upon vga by providing additional features that are used through numerous additional registers. the gmch also supports an optional display cache. as an improvement on the vga standard display cache port-hole, the gmch also maps the entire display cache into part of a single contiguous memory space at a programmable location, providing what is called linear access to the display cache. the size of this memory can be up to 4 mb, and the base address is set via pci configuration registers. alternatively, these buffers may be implemented in system memory (via d.v.m.); this alleviates the need for the display cache. 4.6.7. fixed blitter (blt) and stretch blitter (strblt) engines the gmch s 64-bit blt engine provides hardware acceleration for many common windows* operations. the following are two primary blt functions: fixed blitter (blt) and stretch blitter (strblt). the term blt refers to a block transfer of pixel data between memory locations. the word fixed is used to differentiate from the stretch blt engine. the blt engine can be used for the following: move rectangular blocks of data between memory locations data alignment perform logical operations the internal graphics device of the gmch has instructions to invoke blt and strblt operations, permitting software to set up instruction buffers and use batch processing as described in the 3d/2d instruction processing (pipeline preprocessor) section. note that these instructions replace the need to do pio directly to blt and strblt registers, which speeds up the operation.
intel ? 82810/82810-dc100 (gmch) r 96 datasheet 4.6.7.1. fixed blt engine the rectangular block of data does not change as it is transferred between memory locations. the allowable memory transfers are between: system memory and display cache, display cache and display cache, and system memory and system memory. data to be transferred can consist of regions of memory, patterns, or solid color fills. a pattern is always be 8x8 pixels wide and may be 8, 16, or 24 bits per pixel. the internal graphics device of the gmch has the ability to expand monochrome data into a color depth of 8, 16, or 24 bits. blts can be either opaque or transparent. opaque transfers, move the data specified to the destination. transparent transfers, compare destination color to source color and write according to the mode of transparency selected. data horizontally and vertically aligned at the destination. if the destination for the blt overlaps with the source memory location, the gmch can specify which area in memory to begin the blt transfer. use of this blt engine accelerates the graphical user interface (gui) of microsoft* windows. hardware is included for all 256 raster operations (source, pattern, and destination) defined by microsoft* , including transparent blt. 4.6.7.2. arithmetic stretch blt engine the stretch blt function can stretch source data in the x and y directions to a destination larger or smaller than the source. stretch blt functionality expands a region of memory into a larger or smaller region using replication and interpolation. the stretch blt engine also provides format conversion and data alignment. through an algorithm implemented in the mapping engine, object expansion and contraction can occur in the horizontal and vertical directions. 4.6.8. hardware motion compensation the motion compensation (mc) process consists of reconstructing a new picture by predicting (either forward, backward or bidirectionally) the resulting pixel colors from one or more reference pictures. the gmch intercepts the dvd pipeline at motion compensation and implements motion compensation and subsequent steps in hardware. performing motion compensation in hardware reduces the processor demand of software-based mpeg-2 decoding, and thus improves system performance. the gmchs implementation of hardware motion compensation supports a motion smoothing algorithm. when the system processor is not able to process the mpeg decoding stream in a timely manner (as can happen in software dvd implementations), the gmch supports downsampled mpeg decoding. downsampling allows for reduced spatial resolution in the mpeg picture while maintaining a full frame rate, and thus reduces processor load while maintaining the best video quality possible given the processor constraints.
r intel ? 82810/82810-dc100 (gmch) datasheet 97 4.6.9. hardware cursor the internal graphics device of the gmch allows up to an unlimited number of cursor patterns to be stored in the display cache or system memory. two sets of registers, contain the x and y position of the cursor relative to the upper left corner of the display. the following four cursor modes are provided: 32x32 2 bpp and/xor 2-plane mode 64x64 2 bpp 3-color and transparency mode 64x64 2 bpp and/xor 2-plane mode 64x64 2 bpp 4-color mode 4.6.10. overlay engine the overlay engine provides a method of merging either video capture data (from an external pci video capture adapter) or data delivered by the processor, with the graphics data on the screen. supported data formats include yuv 4:2:2, yuv 4:2:0, yuv 4:1:0, yuv 4:1:1, rgb15, and rgb16. the source data can be mirrored horizontally or vertically or both. overlay data comes from a buffer located system memory. additionally, the overlay engine can be quadruple buffered in order to support flipping between different overlay images. data can either be transferred into the overlay buffer from the host or from an external pci adapter, such as dvd hardware or video capture hardware. buffer swaps can be done by the host and internally synchronized with the display vblank. the internal graphics device of the gmch can accept line widths up to 720 pixels. in addition, overlay source and destination chromakeying are also supported. overlay source/destination chromakeying enables blending of the overlay with the underlying graphics background. destination color/chroma keying can be used to handle occluded portions of the overlay window on a pixel by pixel basis which is actually an underlay. source color/chroma keying is used to handle transparency based on the overlay window on a pixel by pixel basis. this is used when blue screening an image in order to overlay the image on a new background later. to compensate for overlay color intensity loss due to the non-linear response between display devices, the overlay engine supports independent gamma correction. in addition, the brightness, saturation, and contrast of the overlay may be independently varied. 4.6.11. display the display function contains a ram-based digital-to-analog converter (ramdac) that transforms the digital data from the graphics and video subsystems to analog data for the monitor. the gmchs integrated 230 mhz ramdac provides resolution support up to 1600x1200. circuitry is incorporated to limit the switching noise generated by the dacs. three 8-bit dacs provide the r, g, and b signals to the monitor. sync signals are properly delayed to match any delays from the d-to-a conversion. associated with each dac is a 256 pallet of colors. the ramdac can be operated in either direct or indexed color mode. in direct color mode, pixel depths of 15, 16, or 24 bits can be realized. non- interlaced mode is supported. gamma correction can be applied to the display output.
intel ? 82810/82810-dc100 (gmch) r 98 datasheet the gmch supports a wide range of resolutions, color depths, and refresh rates via a programmable dot clock that has a maximum frequency of 230 mhz. table 17. partial list of display modes supported bits per pixel (frequency in hz) resolution 8-bit indexed 16-bit 24-bit 320x200 70 70 70 320x240 70 70 70 352x480 70 70 70 352x576 70 70 70 400x300 70 70 70 512x384 70 70 70 640x400 70 70 70 640x480 60,70,72,75,85 60,70,72,75,85 60,70,72,75,85 720x480 75,85 75,85 75,85 720x576 60,75,85 60,75,85 60,75,85 800x600 60,70,72,75,85 60,70,72,75,85 60,70,72,75,85 1024x768 60, 70,72,75,85 60, 70,72,75,85 60, 70,72,75,85 1152x864 60,70,72,75,85 60,70,72,75,85 60,70,72,75,85 1280x720 60,75,85 60,75,85 60,75,85 1280x960 60,75,85 60,75,85 60,75,85 1280x1024 60,70,72,75,85 60,70,72,75,85 60,70,75,85 1600x900 60,75,85 60,75,85 1600x1200 60,70,72,75,85
r intel ? 82810/82810-dc100 (gmch) datasheet 99 4.6.12. flat panel interface / 1.8v tv-out interface the gmch has a dedicated port for flat panel support. this port is a 16 bit digital port (4 control bits and 12 data bits) with a 1.8v interface for high speed signaling. the port is designed to connect to transmission devices. the port can also be used to interface with an external tv encoder that requires 1.8v signals. connecting the gmch to a flat panel transmitter is demonstrated below. for more details, refer to the intel ? 810 chipset design guide. the gmch supports a variety of flat panel display modes and refresh rates that require up to a 65 mhz dot clock over this interface. table 18 shows some of the display modes supported by the gmch. table 19 shows some of the tv-out modes supported by the gmch. table 18. partial list of flat panel modes supported bits per pixel (frequency in hz) resolution 8-bit indexed 16-bit 24-bit 320x200 1 60 60 60 320x240 1 60 60 60 352x480 1 60 60 60 352x480 1 60 60 60 352x576 1 60 60 60 400x300 1 60 60 60 512x384 1 60 60 60 640x350 1 60 60 60 640x400 1 60 60 60 640x480 1 60 60 60 720x480 1 60 60 60 720x576 1 60 60 60 800x600 1 60 60 60 1024x768 60 60 60 notes: 1. these resolutions are supported via centering.
intel ? 82810/82810-dc100 (gmch) r 100 datasheet table 19. partial list of tv-out modes supported resolution colors ntsc pal 320x200 1 256 yes yes 16m yes yes 64k yes yes 320x240 256 yes yes 16m yes yes 64k yes yes 352x480 1 256 yes yes 16m yes yes 64k yes yes 352x576 1 256 yes yes 16m yes yes 64k yes yes 400x300 1 256 yes yes 16m yes yes 64k yes yes 640x400 1 256 yes yes 640x480 256 yes yes 64k yes yes 16m yes yes 720x480 1 256 yes yes 64k yes yes 16m yes yes 720x576 1 256 yes yes 64k yes yes 16m yes yes 800x600 16 yes yes 256 yes yes 32k yes yes 64k yes yes 16m yes yes notes: 1. these resolutions are supported via centering. 4.6.13. ddc (display data channel) ddc is a standard defined by vesa. its purpose is to allow communication between the host system and display. both configuration and control information can be exchanged allowing plug-and-play systems to be realized. support for ddc 2b is implemented.
r intel ? 82810/82810-dc100 (gmch) datasheet 101 4.7. system reset for the gmch refer to the intel a 810 chipset design guide (power sequencing section) for details. 4.8. system clock description the 810 chipset is supported by a ck810 clock synthesizer. refer to the intel a 810 chipset design guide for details. ck810 features (56 pin ssop package): 3 copies of the processor clock 66 mhz/100 mhz (2.5v) [cpu, gch, itp] 9 copies of 100 mhz (all the time) sdram clock (3.3v) [sdram[0:7], dclk] 8 copies of pci clock (33 mhz ) (3.3v) 2 copies of apic clock @16.67 mhz or 33 mhz, synchronous to processor clock (2.5v) 2 copy of 48 mhz clock (3.3v) [non ssc] 2 copies of 3v66 mhz clock (3.3v) 1 copy of ref clock at 14.31818 mhz (3.3v) also used as input strap to determine apic frequency 66 mhz or 100 mhz processor operation (selectable at power up only) ref. 14.31818 mhz xtal oscillator input power down pin spread spectrum support i 2 c support for turning off unused clocks 4.9. power management 4.9.1. specifications supported the platform is compliant with the following specifications: apm rev 1.2 acpi rev 1.0 pci power management rev 1.0 pc98/99, rev 1.0
intel ? 82810/82810-dc100 (gmch) r 102 datasheet
r intel ? 82810/82810-dc100 (gmch) datasheet 103 5. pinout and package information 5.1. 82810 and 82810-dc100 gmch pinout figure 11 and figure 12 show the ball foot print of the 82810 and 82810-dc100. these figures represent the ballout by ball number. table 20 provides an alphabetical signal listing of the ballout.
intel ? 82810/82810-dc100 (gmch) r 104 datasheet figure 11. gmch pinout (top view-left side) 123456789101112 a vss scke1 scke0 smab7# smaa11 smab5# smaa7 smaa5 smaa2 sdqm1 scas# smd15 b sdqm2 vsus_3.3 scs2# smab6# vss smab4# smaa6 smaa4 vss sdqm4 swe# smd40 c sdqm6 scs3# scs1# scs0# sbs0 smaa9 vsus_3.3 smd47 smaa0 sdqm0 vsus_3.3 smd41 d sdqm3 sdqm7 smd20 vsus_3.3 smaa10 smaa8 smaa3 sras# sdqm5 smd43 smd42 smd38 e smd16 vss smd53 smd52 sbs1 sclk smaa1 smd46 smd45 smd44 vss smd37 f smd49 smd17 smd48 smd54 smd56 vsus_3.3 v_1.8 v_1.8 vsus_3.3 v_1.8 g smd19 smd50 vsus_3.3 smd18 smd57 vss h smd22 smd21 smd51 smd59 smd58 smd60 j smd24 vss smd55 smd23 smd61 vss k smd26 smd25 smd27 smd31 smd62 vsus_3.3 vss vss vss l smd28 smd29 vsus_3.3 vss smd63 vss vss vss m vss reset# smd30 dbsy# gtlrefa vss vss vss n drdy# rs2# ads# htrdy# rs0# vss vss vss p hit# rs1# vss hreq2# hlock# v_1.8 vss vss vss r hitm# hreq3# defer# hreq0# hreq4# vss t bpri# hreq1# bnr# ha7# ha14# vss u ha4# ha8# ha9# ha11# ha3# vccha v ha6# ha16# vss ha5# hd8# hclk v_1.8 v_1.8 v_1.8 v_1.8 w ha10# ha15# ha12# ha13# hd1# vss hd14# hd2# hd16# vss hd32# hd34# y ha28# ha25# ha19# ha30# hd0# hd5# hd18# hd13# hd30# hd26# hd29# hd38# aa ha21# ha18# ha24# vss hd6# hd3# hd12# vss hd7# hd19# hd35# vss ab ha31# ha22# ha20# cpurst# ha26# hd4# hd10# hd20# hd24# hd23# hd25# hd28# ac vss ha17# ha23# ha27# ha29# hd15# hd9# hd11# hd17# hd21# hd33# hd31# notes: 1. an asterisk indicates signals that are only available on the 82810-dc100. for the 82810, these signals are either no connects or used for power-on strapping options.
r intel ? 82810/82810-dc100 (gmch) datasheet 105 figure 12. gmch pinout (top view-right side) 13 14 15 16 17 18 19 20 21 22 23 smd14 smd11 smd8 smd6 smd5 hl7 hl10 hlstrb# hlstrb hl8 hl3 a vss smd10 smd39 smd7 vss hl5 hl4 v_1.8 vss hl2 hl1 b smd13 smd9 vsus_3.3 smd1 smd4 hl6 vss hl9 hl0 lmd23* ldqm2* c smd12 smd34 smd2 smd32 smd3 hcomp hlclk hubref lmd22* lmd20* lmd21* d smd36 smd35 smd33 vss smd0 vss vccba lmd17* lmd18* vss lmd19* e v_1.8 vsus_3.3 v_1.8 v_1.8 v_3.3 lma9* ldqm3* lmd30* lmd31* lmd16* f vss lma8* lmd27* v_3.3 lmd28* lmd29* g lma7* lma5* lma6* lmd24* lmd25* lmd26* h v_3.3 lwe#* lrclk lma4* vss loclk j vss vss vss lras# lcas# lmd4* ltclk lmd5* k vss vss lma11* lcs#* v_3.3 lmd3* lmd2* l vss vss lma0* lma10* lmd1* lmd0* lmd15* m vss vss lma3* lmd14* lmd13* vss lmd12* n vss vss vss lma1* lma2* ldqm0* lmd11* lmd10* p v_3.3 lmd6* lmd7* lmd9* lmd8* ldqm1* r vss ltvcl ltvda ltvdata11 ltvdata10 ltvdata9 t v_1.8 tvhsync tvclkin/ int# ltvdata8 ltvdata7 ltvdata6 u v_1.8 v_1.8 v_1.8 v_1.8 vss blank# tvvsync clkout0 clkout1 ltvdata5 v gtlrefb vss hd52# hd57# hd54# hd56# ddcsda ddcscl ltvdata4 ltvdata3 ltvdata2 w hd37# hd42# hd47# hd59# hd46# hd61# vss ltvdata1 ltvdata0 vss iwaste y hd36# hd44# hd40# vss hd55# hd50# vss vsync dclkref vssda iref aa hd22# hd45# hd51# hd27# hd63# hd53# hd60# hsync vccdaca2 vssdaca vccdaca1 ab hd43# hd39# hd41# hd49# hd48# hd62# hd58# vccda red green blue ac notes: 1. an asterisk indicates signals that are only available on the 82810-dc100. for the 82810, these signals are either no connects or used for power-on strapping options.
intel ? 82810/82810-dc100 (gmch) r 106 datasheet table 20. alphabetical pin assignment pin name ball # ads# n3 blank# v19 blue ac23 bnr# t3 bpri# t1 clkout0 v21 clkout1 v22 cpurst# ab4 dbsy# m4 dclkref aa21 ddcscl w20 ddcsda w19 defer# r3 drdy# n1 green ac22 gtlrefa m5 gtlrefb w13 ha3# u5 ha4# u1 ha5# v4 ha6# v1 ha7# t4 ha8# u2 ha9# u3 ha10# w1 ha11# u4 ha12# w3 ha13# w4 ha14# t5 ha15# w2 ha16# v2 ha17# ac2 ha18# aa2 ha19# y3 pin name ball # ha20# ab3 ha21# aa1 ha22# ab2 ha23# ac3 ha24# aa3 ha25# y2 ha26# ab5 ha27# ac4 ha28# y1 ha29# ac5 ha30# y4 ha31# ab1 hclk v6 hcomp d18 hd0# y5 hd1# w5 hd2# w8 hd3# aa6 hd4# ab6 hd5# y6 hd6# aa5 hd7# aa9 hd8# v5 hd9# ac7 hd10# ab7 hd11# ac8 hd12# aa7 hd13# y8 hd14# w7 hd15# ac6 hd16# w9 hd17# ac9 hd18# y7 hd19# aa10 pin name ball # hd20# ab8 hd21# ac10 hd22# ab13 hd23# ab10 hd24# ab9 hd25# ab11 hd26# y10 hd27# ab16 hd28# ab12 hd29# y11 hd30# y9 hd31# ac12 hd32# w11 hd33# ac11 hd34# w12 hd35# aa11 hd36# aa13 hd37# y13 hd38# y12 hd39# ac14 hd40# aa15 hd41# ac15 hd42# y14 hd43# ac13 hd44# aa14 hd45# ab14 hd46# y17 hd47# y15 hd48# ac17 hd49# ac16 hd50# aa18 hd51# ab15 hd52# w15 hd53# ab18 pin name ball # hd54# w17 hd55# aa17 hd56# w18 hd57# w16 hd58# ac19 hd59# y16 hd60# ab19 hd61# y18 hd62# ac18 hd63# ab17 hit# p1 hitm# r1 hl0 c21 hl1 b23 hl2 b22 hl3 a23 hl4 b19 hl5 b18 hl6 c18 hl7 a18 hl8 a22 hl9 c20 hl10 a19 hlclk d19 hlock# p5 hlstrb a21 hlstrb# a20 hreq0# r4 hreq1# t2 hreq2# p4 hreq3# r2 hreq4# r5 hsync ab20 htrdy# n4
r intel ? 82810/82810-dc100 (gmch) datasheet 107 pin name ball # hubref d20 iref aa23 iwaste y23 lcas# k20 lcs#* l20 ldqm0* p21 ldqm01* r23 ldqm02* c23 ldqm03* f20 lma0* m19 lma1* p19 lma2* p20 lma3* n19 lma4* j21 lma5* h19 lma6* h20 lma7* h18 lma8* g19 lma9* f19 lma10* m20 lma11* l19 lmd0* m22 lmd1* m21 lmd2* l23 lmd3* l22 lmd4* k21 lmd5* k23 lmd6* r19 lmd7* r20 lmd8* r22 lmd9* r21 lmd10* p23 lmd11* p22 lmd12* n23 lmd13* n21 lmd14* n20 pin name ball # lmd15* m23 lmd16* f23 lmd17* e20 lmd18* e21 lmd19* e23 lmd20* d22 lmd21* d23 lmd22* d21 lmd23* c22 lmd24* h21 lmd25* h22 lmd26* h23 lmd27* g20 lmd28* g22 lmd29* g23 lmd30* f21 lmd31* f22 loclk j23 lras# k19 lrclk j20 ltclk k22 ltvcl t19 ltvda t20 ltvdata0 y21 ltvdata1 y20 ltvdata2 w23 ltvdata3 w22 ltvdata4 w21 ltvdata5 v23 ltvdata6 u23 ltvdata7 u22 ltvdata8 u21 ltvdata9 t23 ltvdata10 t22 ltvdata11 t21 lwe#* j19 pin name ball # red ac21 reset# m2 rs0# n5 rs1# p2 rs2# n2 sbs0 c5 sbs1 e5 scas# a11 scke0 a3 scke1 a2 sclk e6 scs0# c4 scs1# c3 scs2# b3 scs3# c2 sdqm0 c10 sdqm1 a10 sdqm2 b1 sdqm3 d1 sdqm4 b10 sdqm5 d9 sdqm6 c1 sdqm7 d2 smaa0 c9 smaa1 e7 smaa2 a9 smaa3 d7 smaa4 b8 smaa5 a8 smaa6 b7 smaa7 a7 smaa8 d6 smaa9 c6 smaa10 d5 smaa11 a5 smab4# b6 pin name ball # smab5# a6 smab6# b4 smab7# a4 smd0 e17 smd1 c16 smd2 d15 smd3 d17 smd4 c17 smd5 a17 smd6 a16 smd7 b16 smd8 a15 smd9 c14 smd10 b14 smd11 a14 smd12 d13 smd13 c13 smd14 a13 smd15 a12 smd16 e1 smd17 f2 smd18 g4 smd19 g1 smd20 d3 smd21 h2 smd22 h1 smd23 j4 smd24 j1 smd25 k2 smd26 k1 smd27 k3 smd28 l1 smd29 l2 smd30 m3 smd31 k4 smd32 d16
intel ? 82810/82810-dc100 (gmch) r 108 datasheet pin name ball # smd33 e15 smd34 d14 smd35 e14 smd36 e13 smd37 e12 smd38 d12 smd39 b15 smd40 b12 smd41 c12 smd42 d11 smd43 d10 smd44 e10 smd45 e9 smd46 e8 smd47 c8 smd48 f3 smd49 f1 smd50 g2 smd51 h3 smd52 e4 smd53 e3 smd54 f4 smd55 j3 smd56 f5 smd57 g5 smd58 h5 smd59 h4 smd60 h6 smd61 j5 smd62 k5 smd63 l5 sras# d8 swe# b11 tvclkin/ int# u20 tvhsync u19 tvvsync v20 pin name ball # v_1.8 p6 v_1.8 f7 v_1.8 v7 v_1.8 f8 v_1.8 v8 v_1.8 v9 v_1.8 f10 v_1.8 v10 v_1.8 f14 v_1.8 v14 v_1.8 v15 v_1.8 f16 v_1.8 v16 v_1.8 f17 v_1.8 v17 v_1.8 u18 v_1.8 b20 v_3.3 f18 v_3.3 j18 v_3.3 r18 v_3.3 g21 v_3.3 l21 vccba e19 vccda ac20 vccdaca1 ab23 vccdaca2 ab21 vccha u6 vss a1 vss m1 vss ac1 vss e2 vss j2 vss p3 vss v3 vss l4 vss aa4 pin name ball # vss b5 vss g6 vss j6 vss r6 vss t6 vss w6 vss aa8 vss b9 vss k10 vss l10 vss m10 vss n10 vss p10 vss w10 vss e11 vss k11 vss l11 vss m11 vss n11 vss p11 vss k12 vss l12 vss m12 vss n12 vss p12 vss aa12 vss b13 vss k13 vss l13 vss m13 vss n13 vss p13 vss k14 vss l14 vss m14 vss n14 pin name ball # vss p14 vss w14 vss e16 vss aa16 vss b17 vss e18 vss g18 vss k18 vss p18 vss t18 vss v18 vss c19 vss y19 vss aa19 vss b21 vss e22 vss j22 vss n22 vss y22 vssda aa22 vssdaca ab22 vsus_3.3 b2 vsus_3.3 g3 vsus_3.3 l3 vsus_3.3 d4 vsus_3.3 f6 vsus_3.3 k6 vsus_3.3 c7 vsus_3.3 f9 vsus_3.3 c11 vsus_3.3 c15 vsus_3.3 f15 vsync aa20
r intel ? 82810/82810-dc100 (gmch) datasheet 109 5.2. package dimensions this section shows the mechanical dimensions for the 82810 and 82810-dc100 devices. the package is a 421 ball grid array (bga). figure 13. gmch package dimensions (421 bga) C top and side views pin a1 i.d. pin a1 corner d d1 e e1 top view a a2 a1 c side view 421_pk g 1.vsd seatin g plane -c- 45 chamfer (4 places) 30
intel ? 82810/82810-dc100 (gmch) r 110 datasheet figure 14. gmch package dimensions (421 bga) C bottom view 421_pkg2.vsd pin a1 corner b e 421 bga bottom view j l 2 10 16 20 22 3 5 7 9 11 13 15 17 19 1 21 23 4 6 18 8 12 14 a b c d e f g h j k l p r t u v y ab aa ac n w m e table 21. gmch package dimensions (421 bga) symbol min nominal max units note a 2.17 2.38 2.59 mm a1 0.50 0.60 0.70 mm a2 1.12 1.17 1.22 mm d 30.80 31.00 31.20 mm d1 25.80 26.00 26.20 mm e 30.90 31.00 31.10 mm e1 25.80 26.00 26.20 mm e 1.27 (solder ball pitch) mm i 1.53 ref. mm j 1.53 ref. mm m 23 x 23 matrix mm b 2 0.60 0.75 0.90 mm c 0.55 0.61 0.67 mm notes: notes: 1. all dimensions and tolerances conform to ansi y14.5-1982 2. dimension is measured at maximum solder ball diameter parallel to primary datum (-c-) 3. primary datum (-c-) and seating plane are defined by the spherical crowns of the solder balls.
r intel ? 82810/82810-dc100 (gmch) datasheet 111 6. testability in the gmch, the testability for automated test equipment (ate) board level testing has been changed from the traditional nand chain mode to a xor chain. the gmch pins are grouped in seven xor chains. an xor-tree is a chain of xor gates each with one of its inputs connected to a gmch input pin or bi- directional pin (used as an input pin only). the other input of each xor gate connects to the non- inverted output of the previous xor gate in the chain. the first xor gate of each chain has one pin internally connected to vcc. the output of the last xor gate is the chain output. figure 15 shows the gmch xor chain implementation. figure 15. xor tree implementation vcc pin 1 xor out xor.vsd pin 2 pin 3 pin 4 pin 5 pin 6 tri-state gmch outputs when testing other devices in the system, the gmch outputs can be tri-stated. to tri-state these outputs pull the lmd30 pin high (3.3v) prior to deasserting reset#. the following sequence puts the gmch into tri-state mode: 1. deassert reset# high and lmd30 high 2. assert reset# low; maintain lmd30 high 3. deassert reset# high; maintain lmd30 high 4. reset# must be maintained high for the duration of testing. no external clocking of the gmch is required.
intel ? 82810/82810-dc100 (gmch) r 112 datasheet 6.1. xor tree testability algorithm example xor tree testing allows users to check, for example, opens and shorts to vcc or gnd. an example algorithm to do this is shown in table 22. table 22. xor test pattern example pin # from figure 15 vector pin1 pin2 pin3 pin4 pin5 pin6 xorout 10000001 21000000 31100001 41110000 51111001 61111100 71111111 in this example, vector 1 applies all 0s to the chain inputs. the outputs being non-inverting, consistently produce a 1 at the xor chain output on a good board. one short to vcc (or open floating to vcc) causes a 0 at the chain output, signalling a defect. likewise, applying vector 7 (all 1) to chain inputs (given that there are an even number of signals in the chain), consistently produce a 1 at the xor chain output on a good board. one short to vss (or open floating to vss) causes a 0 at the chain output, signalling a defect. it is important to note that the number of inputs pulled to 1 affect the expected chain output value. if the number chain inputs pulled to 1 is even, then expect 1 at xor-out; otherwise, if odd, expect 0. continuing to illustrate with the example pattern in table 22, as the pins are driven to 1 across the chain in sequence, xor-out toggles between 0 and 1. any break in the toggling sequence (e.g., 1011) identifies the location of the short or open. 6.1.1. test pattern consideration for xor chain 7 bi-directional pins hlstrb (chain 7) and hlstrb# (chain 6) must always be complementary to each other. for example, if a 1 is driven on to hlstrb, a 0 must be driven on hlstrb# and vice versa. this needs to be considered in applying test patterns to this chain.
r intel ? 82810/82810-dc100 (gmch) datasheet 113 6.2. xor tree initialization 6.2.1. chain [1:2, 4:7] initialization on chains [1:2,4:7], all that is required to prepare the device for xor chain testing is to pull lmd31 high (+3.3v) prior to the deasserting reset#. lmd31 must be brought back to a low state after this sequence, as this pin is part of xor chain 2. the following sequence puts the gmch into xor testability mode: 1. deassert reset# high and lmd31 (high) 2. assert reset# low; maintain lmd31 (high) 3. deassert reset# high; maintain lmd31 (high) 4. reset# must be maintained high for the duration of testing. no external clocking of the gmch is required for testing these chains. 6.2.2. chain 3 initialization to test xor chain 3, a different initialization sequence is required. the following steps need to be implemented: 1. provide clocks at a minimum frequency of 10 mhz to the gmch host clock (hclk), hub interface clock (hlclk), and display interface clock (dclkref). phase relationship between hclk and hlclk must be maintained such that they are 180 degrees out of phase, and their edges line up within 400 ps. 2. deassert reset# high and assert lmd31 high 3. assert reset# low for 35,000 hlclks; maintain lmd31 high 4. deassert reset# high for 35,000 hlclks; maintain lmd31 high 5. chain #3 is now initialized and ready to begin xor test. reset# must be maintained high for the duration of testing.
intel ? 82810/82810-dc100 (gmch) r 114 datasheet 6.3. xor chain pin assignments table 23. xor chain 1 pin name ball# voltage lmd6 (start) r19 3.3v lmd7 r20 3.3v lmd9 r21 3.3v lmd8 r22 3.3v lma1 p19 3.3v ldqm1 r23 3.3v lma2 p20 3.3v ldqm0 p21 3.3v lmd11 p22 3.3v lmd10 p23 3.3v lma3 n19 3.3v lmd14 n20 3.3v lmd13 n21 3.3v lmd12 n23 3.3v lmd15 m23 3.3v lmd0 m22 3.3v lmd1 m21 3.3v lma0 m19 3.3v lcas# k20 3.3v lma4 j21 3.3v lma5 h19 3.3v lmd21 d23 3.3v lmd18 e21 3.3v lmd20 d22 3.3v lmd17 e20 3.3v lmd22 d21 3.3v lmd23 (end) c22 3.3v length = 27 chain 1 output lras# k19 3.3v notes: 1. chain 1 = odd number of xor gates: all 1s yields lras# = 0 table 24. xor chain 2 pin name ball # voltage lma10 (start) m20 3.3v lmd2 l23 3.3v lmd3 l22 3.3v lcs# l20 3.3v lma11 l19 3.3v lmd5 k23 3.3v ltclk k22 3.3v lmd4 k21 3.3v loclk j23 3.3v lmd26 h23 3.3v lrclk j20 3.3v lmd25 h22 3.3v lmd24 h21 3.3v lmd29 g23 3.3v lma6 h20 3.3v lmd28 g22 3.3v lmd16 f23 3.3v lmd31 f22 3.3v lmd27 g20 3.3v lmd19 e23 3.3v lmd30 f21 3.3v lma7 h18 3.3v lma8 g19 3.3v ldqm3 f20 3.3v ldqm2 c23 3.3v lma9 (end) f19 3.3v length = 26 chain 2 output lwe# j19 3.3v notes: 1. chain 2 = even number of xor gates: all 1s yields lwe# = 1
r intel ? 82810/82810-dc100 (gmch) datasheet 115 table 25. xor chain 3 pin name ball# voltage blank# v19 1.8v ltvdata1 y20 1.8v tvvsync v20 1.8v tvhsync u19 1.8v ltvdata4 w21 1.8v ltvdata3 w22 1.8v clkout0 v21 1.8v ltvdata2 w23 1.8v clkout1 v22 1.8v ltvdata8 u21 1.8v ltvdata5 v23 1.8v ltvdata7 u22 1.8v ltvdata6 u23 1.8v ltvdata11 t21 1.8v ltvdata10 t22 1.8v ltvdata9 t23 1.8v tvclkin u20 1.8v vsync aa20 3.3v hsync ab20 3.3v ltvda t20 3.3v ltvcl t19 3.3v ddcscl w20 3.3v ddcsda w19 3.3v ha29# ac5 1.5v hd32# w11 1.5v hd35# aa11 1.5v hd33# ac11 1.5v hd38# y12 1.5v hd34# w12 1.5v hd43# ac13 1.5v hd36# aa13 1.5v hd37# y13 1.5v hd39# ac14 1.5v hd45# ab14 1.5v hd44# aa14 1.5v table 25. xor chain 3 pin name ball# voltage hd42# y14 1.5v hd41# ac15 1.5v hd51# ab15 1.5v hd40# aa15 1.5v hd47# y15 1.5v hd49# ac16 1.5v hd52# w15 1.5v hd48# ac17 1.5v hd59# y16 1.5v hd63# ab17 1.5v hd62# ac18 1.5v hd55# aa17 1.5v hd57# w16 1.5v hd53# ab18 1.5v hd46# y17 1.5v hd58# ac19 1.5v hd50# aa18 1.5v hd54# w17 1.5v hd60# ab19 1.5v hd61# y18 1.5v hd56# w18 1.5v length = 56 chain 3 output ltvdata0 y21 1.8v notes: 1. chain 3 = even number of xor gates: all 1s yields ltvdata0 = 1
intel ? 82810/82810-dc100 (gmch) r 116 datasheet table 26. xor chain 4 pin name ball# voltage hd27# (start) ab16 1.5v ha14# t5 1.5v ha16# v2 1.5v ha11# u4 1.5v ha10# w1 1.5v ha3# u5 1.5v ha15# w2 1.5v ha28# y1 1.5v ha5# v4 1.5v ha12# w3 1.5v ha25# y2 1.5v ha21# aa1 1.5v hd8# v5 1.5v ha13# w4 1.5v ha19# y3 1.5v ha18# aa2 1.5v ha31# ab1 1.5v ha24# aa3 1.5v ha22# ab2 1.5v hd1# w5 1.5v ha30# y4 1.5v ha17# ac2 1.5v ha20# ab3 1.5v hd0# y5 1.5v ha23# ac3 1.5v cpurst# ab4 1.5v hd6# aa5 1.5v hd5# y6 1.5v ha27# ac4 1.5v ha26# ab5 1.5v hd14# w7 1.5v hd3# aa6 1.5v hd18# y7 1.5v hd4# ab6 1.5v hd2# w8 1.5v table 26. xor chain 4 pin name ball# voltage hd12# aa7 1.5v hd15# ac6 1.5v hd10# ab7 1.5v hd13# y8 1.5v hd9# ac7 1.5v hd16# w9 1.5v hd20# ab8 1.5v hd30# y9 1.5v hd11# ac8 1.5v hd7# aa9 1.5v hd24# ab9 1.5v hd17# ac9 1.5v hd26# y10 1.5v hd19# aa10 1.5v hd23# ab10 1.5v hd21# ac10 1.5v hd29# y11 1.5v hd25# ab11 1.5v hd31# ac12 1.5v hd28# ab12 1.5v hd22# ab13 1.5v length =56 chain 4 output sdqm3 d1 3.3v notes: 1. chain 4 = even number of xor gates: all 1s yields sdqm3 = 1
r intel ? 82810/82810-dc100 (gmch) datasheet 117 table 27. xor chain 5 pin name ball# voltage sdqm1 (start) a10 3.3v sdqm0 c10 3.3v smaa2 a9 3.3v smd45 e9 3.3v smd47 c8 3.3v smaa5 a8 3.3v smaa4 b8 3.3v smab#7 a4 3.3v smab#6 b4 3.3v scke0 a3 3.3v scke1 a2 3.3v smaa1 e7 3.3v smaa3 d7 3.3v smd46 e8 3.3v sbs0 c5 3.3v smd56 f5 3.3v scs0# c4 3.3v smd57 g5 3.3v scsb1 c3 3.3v smd52 e4 3.3v smd20 d3 3.3v smd54 f4 3.3v smd53 e3 3.3v smd58 h5 3.3v sdqm2 b1 3.3v smd18 g4 3.3v smd60 h6 3.3v smd48 f3 3.3v smd63 l5 3.3v smd29 l2 3.3v smd28 l1 3.3v smd30 m3 3.3v dbsy# m4 1.5v drdy# n1 1.5v rs2# n2 1.5v table 27. xor chain 5 pin name ball# voltage ads# n3 1.5v htrdy# n4 1.5v rs0# n5 1.5v hit# p1 1.5v rs1# p2 1.5v hreq2# p4 1.5v hitm# r1 1.5v hlock# p5 1.5v hreq3# r2 1.5v defer# r3 1.5v bpri# t1 1.5v hreq0# r4 1.5v hreq1# t2 1.5v hreq4# r5 1.5v bnr# t3 1.5v ha4# u1 1.5v ha7# t4 1.5v ha8# u2 1.5v ha6# v1 1.5v ha9# u3 1.5v length = 55 chain 5 output smaa0 c9 3.3v notes: 1. chain 5 = odd number of xor gates: all 1s yields smaa0 = 0
intel ? 82810/82810-dc100 (gmch) r 118 datasheet table 28. xor chain 6 pin name ball# voltage hlstrb#(start) a20 1.8v smd8 a15 3.3v smd34 d14 3.3v smd9 c14 3.3v smd10 b14 3.3v smd11 a14 3.3v smd36 e13 3.3v smd12 d13 3.3v smd13 c13 3.3v smd14 a13 3.3v smd37 e12 3.3v smd38 d12 3.3v smd41 c12 3.3v smd40 b12 3.3v smd15 a12 3.3v scas# a11 3.3v smd42 d11 3.3v sdqm4 b10 3.3v smd43 d10 3.3v smd44 e10 3.3v sdqm5 d9 3.3v sras# d8 3.3v smaa7 a7 3.3v smaa6 b7 3.3v smab5# a6 3.3v smab4# b6 3.3v smaa11 a5 3.3v smaa9 c6 3.3v smaa8 d6 3.3v smaa10 d5 3.3v sbs1 e5 3.3v scs3# c2 3.3v sdqm7 d2 3.3v sdqm6 c1 3.3v smd59 h4 3.3v table 28. xor chain 6 pin name ball# voltage smd17 f2 3.3v smd16 e1 3.3v smd23 j4 3.3v smd51 h3 3.3v smd50 g2 3.3v smd49 f1 3.3v smd61 j5 3.3v smd19 g1 3.3v smd31 k4 3.3v smd55 j3 3.3v smd21 h2 3.3v smd62 k5 3.3v smd22 h1 3.3v smd24 j1 3.3v smd27 k3 3.3v smd25 k2 3.3v smd26 k1 3.3v length =53 chain 6 output scs2# b3 3.3v notes: 1. chain 6 = odd number of xor gates: all 1s yields scs2# = 1
r intel ? 82810/82810-dc100 (gmch) datasheet 119 table 29. xor chain 7 pin name ball# voltage hl1 (start) b23 1.8v hl3 a23 1.8v hl2 b22 1.8v hl0 c21 1.8v hl8 a22 1.8v hl9 c20 1.8v hlstrb a21 1.8v hl4 b19 1.8v hcomp d18 1.8v hl10 a19 1.8v hl6 c18 1.8v hl5 b18 1.8v hl7 a18 1.8v smd0 e17 3.3v smd3 d17 3.3v table 29. xor chain 7 pin name ball# voltage smd4 c17 3.3v smd32 d16 3.3v smd5 a17 3.3v smd1 c16 3.3v smd33 e15 3.3v smd7 b16 3.3v smd2 d15 3.3v smd6 a16 3.3v smd39 b15 3.3v smd35 e14 3.3v length=25 chain 7 output swe# b11 3.3v notes: 1. chain 7 = odd number of xor gates: all 1s yields swe# = 1
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